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Data Sheet

AD7383-4/AD7384-4

THEORY OF OPERATION

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Rev. 0 | 15 of 33

CIRCUIT INFORMATION

The AD7383-4/AD7384-4 are high speed, quad, pseudo differential,

16-bit and 14-bit (respectively), SAR ADCs. The devices operate

from a 3.0 V to 3.6 V power supply and feature throughput rates up

to 4 MSPS.

The AD7383-4/AD7384-4 contain four successive approximation

ADCs and serial peripheral interfaces (SPIs) with four separate da-

ta output pins. The devices are housed in a 24-lead LFCSP, offering

the user considerable space-saving advantages over alternative

solutions.

Data is accessed from the devices via the SPI. The SPI can oper-

ate with two, four, or one serial output(s). The AD7383-4/AD7384-4

have an on-chip 2.5 V internal reference (VREF). If an external

reference voltage is required, and the values range from 2.5 V to

3.3 V, set the REFSEL bit in the CONFIGURATION1 register to 1.

If the internal reference is used elsewhere in the system, buffer the

reference output. The pseudo differential analog input range for the

AD7383-4/AD7384-4 is the common-mode voltage (VCM) ± VREF/2.

The AD7383-4/AD7384-4 feature on-chip oversampling blocks to

improve performance. Normal averaging and rolling average over-

sampling modes are available. Power-down options to allow power

saving between conversions are available. Configuration of the

devices is implemented via the standard SPI, as described in the

Interface section.

CONVERTER OPERATION

The AD7383-4/AD7384-4 have four successive approximation

ADCs, each based around two capacitive DACs. Figure 24 and

Figure 25 show simplified schematics of one of these ADCs in

acquisition phase and conversion phase, respectively. The ADC

comprises control logic, an SAR, and two capacitive DACs. In

Figure 24 (the acquisition phase), SW3 is closed, SW1 and SW2

are in Position A, the comparator is held in a balanced condition,

and the sampling capacitor (CS) arrays can acquire the differential

signal on the input.

Figure 24. ADC Acquisition Phase

When the ADC starts a conversion (see Figure 25), SW3 opens

and SW1 and SW2 move to Position B, causing the comparator

to become unbalanced. Both inputs are disconnected when the

conversion begins. The control logic and charge redistribution

DACs are used to add and subtract fixed amounts of charge from

the sampling capacitor arrays to bring the comparator back into

a balanced condition. When the comparator is rebalanced, the

conversion is complete. The control logic generates the ADC output

code. Match the output impedance of the sources driving the AINx+

and AINx− pins. Otherwise, the two inputs have different settling

times, resulting in errors.

Figure 25. ADC Conversion Phase

ANALOG INPUT STRUCTURE

Figure 26 shows the equivalent circuit of the analog input structure

of the AD7383-4/AD7384-4. The four diodes provide ESD protec-

tion for the analog inputs. Ensure that the analog input signals

never exceed the supply rails by more than 300 mV. Exceeding

the limit causes these diodes to become forward biased and start

conducting into the substrate. These diodes can conduct up to 10

mA without causing irreversible damage to the devices.

The C1 capacitors in Figure 26 are typically 3 pF and are primarily

attributed to pin capacitance. The R1 resistors are lumped compo-

nents made up of the on resistance of the switches. The value of

these resistors is typically 200 Ω. The C2 capacitors are the ADC

sampling capacitors with a typical capacitance of 15 pF.

Figure 26. Equivalent Analog Input Circuit, Conversion Phase—Switches

Open, Track Phase—Switches Closed

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