Data Sheet

AD7383-4/AD7384-4

REGISTERS

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Rev. 0 | 28 of 33

The AD7383-4/AD7384-4 have user-programmable on-chip registers for configuring the device. Table 16 shows a complete overview of the

registers available on the AD7383-4/AD7384-4.

The registers are either read/write (R/W) or read only (R). Any read request to a write only register is ignored, and any write request to a read

only register is ignored. Writes to the NOP registers and the reserved register are ignored. Any read request to the NOP registers or reserved

registers is considered an NOP, and the data transmitted in the next SPI frame are the conversion results.

Table 16. Register Description

Reg

Name

Bits

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default

R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x1

CONFIGURATIO

N1

[15:8]

WR

ADDRESSING

RESERVED

OS_MODE

OSR, Bit 2

0x0000

R/W

[7:0]

OSR, Bits[1:0]

CRC_W

CRC_R

ALERT_EN RES

REFSEL

PMODE

0x2

CONFIGURATIO

N2

[15:8]

WR

ADDRESSING

RESERVED

SDO, Bits[1:0]

0x0000

R/W

[7:0]

RESET, Bits[7:0]

0x3

ALERT

[15:8]

WR

ADDRESSING

RESERVED

CRCW_F

SETUP_F

0x0000

R

[7:0]

AI_D_HIGH AI_D_LOW AI_C_HIGH AI_C_LOW AI_B_HIGH AI_B_LOW AI_A_HIGH AI_A_LOW

0x4

ALERT_LOW_T

HRESHOLD

[15:8]

WR

ADDRESSING

ALERT_LOW, Bits[11:8]

0x0800

R

[7:0]

ALERT_LOW, Bits[7:0]

0x5

ALERT_HIGH_T

HRESHOLD

[15:8]

WR

ADDRESSING

ALERT_HIGH, Bits[11:8]

0x07FF

R/W

[7:0]

ALERT_HIGH, Bits[7:0]

ADDRESSING REGISTERS

A serial register transfer on the AD7383-4/AD7384-4 consists of 16 SCLK cycles. The 4 MSBs written to the device are decoded to determine

which register is addressed and consist of the register address (REGADDR), Bits[2:0], and the read/write bit (WR). The register address bits

determine which on-chip register is selected. If the addressed register is a valid write register, the WR bit determines whether the remaining 12

bits of data on the SDI input are loaded into the addressed register. If the WR bit is 1, the bits load into the register addressed by the register

select bits. If the WR bit is 0, the command is seen as a read request, and the addressed register data is available to be read during the next

read operation.

Table 17. Addressing Register Format

MSB

LSB

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

WR

REGADDR, Bits[2:0]

Data, Bits[11:0]

Table 18. Bit Descriptions for Addressing Registers

Bit

Mnemonic

Description

D15

WR

When a 1 is written to this bit, Bits[11:0] of this register are written to the register specified by REGADDR if it is a valid address.

Alternatively, when a 0 is written, the next data sent out on the SDOA pin is a read from the designated register if it is a valid address.

D14 to D12

REGADDR

When WR = 1, the contents of REGADDR determine the register for selection as outlined in Table 16.

When WR = 0 and the REGADDR bits contain a valid register address, the contents on the requested register are output on the SDOA

pin during the next interface access.

When WR = 0 and the REGADDR bits contain 0x0, 0x6, or 0x7, the contents on the SDI line are ignored. The next interface access

results in the conversion results being read back.

D11 to D0

DATA

The DATA bits are written into the corresponding register specified by the REGADDR bits when the WR bit = 1 and the REGADDR bits

contain a valid address.

CONFIGURATION1 REGISTER

Address: 0x1, Reset: 0x0000, Name: CONFIGURATION1