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Data Sheet

AD7383-4/AD7384-4

MODES OF OPERATION

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RESOLUTION BOOST

The default resolution and output data size are 16 bits for the

AD7383-4 and 14 bits for the AD7384-4. When the on-chip over-

sampling function is enabled, the performance of the ADC can

exceed the default resolution. To accommodate the performance

boost achievable, it is possible to enable an additional two bits of

resolution. If the RES bit in the CONFIGURATION1 register is set

to Logic 1 and the AD7383-4/AD7384-4 are in a valid oversampling

mode, the conversion result size for the AD7383-4 is 18 bits and

the AD7384-4 is 16 bits. In this mode, 18 SCLK cycles are required

to propagate the data for the AD7383-4 and 16 SCLK cycles are

required for the AD7384-4.

ALERT

The alert functionality is an out of range indicator and can

be used as an early indicator of an out of bounds con-

version result. An alert event triggers when the value in

the conversion result register exceeds the alert high limit

value in the ALERT_HIGH_THRESHOLD register or falls be-

low the alert low limit value in the ALERT_LOW_THRESH-

OLD register. The ALERT_HIGH_THRESHOLD register and the

ALERT_LOW_THRESHOLD register are common to all ADCs.

When setting the threshold limits, the alert high threshold must

always be greater than the alert low threshold. Detailed alert infor-

mation is accessible in the ALERT indication register.

The register contains two status bits per ADC, one corresponding

to the high limit, and the other to the low limit. A logical OR of alert

signals for all ADCs create a common alert value. This value can be

configured to drive out on the ALERT function of the SDOD/ALERT

pin. The SDOD/ALERT pin is configured as ALERT by configuring

the bits in CONFIGURATION1 and CONFIGURATION2 as follows:

1. Set the SDO bit to any value other than 0b10.

2. Set the ALERT_EN bit to 1.

3. Set a valid value in the ALERT_HIGH_THRESHOLD register

and the ALERT_LOW_THRESHOLD register.

The alert indication function is available in oversampling (rolling

average, normal averaging, and in non-oversampling modes).

The alert function of the SDOD/ALERT pin updates at the end of

conversion. The alert indication status bits in the ALERT register

are updated as well and must be read before the end of the next

conversion.

Bits[7:0] in the alert indication register are cleared by reading the

alert indication register contents. The alert function of the SDOD/

ALERT pin is cleared with a falling edge of CS. Issuing a software

reset also clears the alert status in the alert indication register.

See Figure 8 for the ALERT timing diagram.

Figure 31. Resolution Boost

POWER MODES

The AD7383-4/AD7384-4 have two power modes that can be set in

the CONFIGURATION1 register, normal mode and shutdown mode.

These modes of operation provide flexible power management op-

tions, allowing optimization of the power dissipation and throughput

rate ratio for different application requirements.

Program the PMODE bit in the CONFIGURATION1 register to con-

figure the power modes in the AD7383-4/AD7384-4. Set PMODE to

Logic 0 for normal mode and Logic 1 for shutdown mode.

Normal Mode

Keep the AD7383-4/AD7384-4 in normal mode to achieve the

fastest throughput rate. All blocks within the AD7383-4/AD7384-4

remain fully powered, and an ADC conversion can be initiated by

a falling edge of CS when required. When the AD7383-4/AD7384-4

are not converting, the devices are in static mode and power

consumption is automatically reduced. Additional current is required

to perform a conversion. Therefore, power consumption of the

AD7383-4/AD7384-4 scales with throughput.

Shutdown Mode

When slower throughput rates and lower power consumption are

required, use shutdown mode by either powering down the ADC

between each conversion or by performing a series of conversions

at a high throughput rate and then powering down the ADC for

a relatively long duration between these burst conversions. When

the AD7383-4/AD7384-4 are in shutdown mode, all analog circuitry

powers down. The SPI remains active during shutdown mode to

allow the AD7383-4/AD7384-4 to exit shutdown mode.

To enter shutdown mode, write to the PMODE bit in the CON-

FIGURATION1 register. The AD7383-4/AD7384-4 shuts down and

current consumption reduces.

To exit shutdown mode and return to normal mode, set the PMODE

bit in the CONFIGURATION1 register to Logic 0. All register config-

uration settings remain unchanged entering or leaving shutdown

mode. After exiting shutdown mode, allow sufficient time for the

circuitry to turn on before starting a conversion.

INTERNAL AND EXTERNAL REFERENCE

The AD7383-4/AD7384-4 have a buffered 2.5 V internal reference

primarily used for internal device operation and access via the

REFIO pin. When using the buffered internal 2.5 V reference exter-

nally, the reference must use an external buffer before connecting

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