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AM625 Datasheet(PDF) 85 Page - Texas Instruments |
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AM625 Datasheet(HTML) 85 Page - Texas Instruments |
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85 / 259 page  Table 6-74. Connectivity Requirements (continued) ALW BALL NUMBER AMC BALL NUMBER BALL NAME CONNECTION REQUIREMENTS N6 R3 M4 T1 M5 N3 J1 J2 K3 L5 K4 K1 R2 P2 P1 P4 R5 P5 R6 R1 M1 N1 T4 N2 M2 L1 L2 H2 J4 L6 K2 H5 W5 F4 G5 F3 H6 E3 G2 F2 F1 U1 U3 U2 V5 W2 V6 Y1 W1 E1 E2 V1 V2 H1 J3 G1 M1 N1 J3 M2 K5 J2 F5 G5 G4 H4 J5 H5 P4 N2 P2 N4 N3 M3 P5 N5 L5 L3 L4 L2 K4 J1 K1 G3 H2 H3 G1 E3 R4 C2 E4 D3 E5 D2 F3 F1 F2 R3 R2 T2 U2 U3 U4 T4 T5 D1 E1 T1 R1 J4 K2 G2 DDR0_ACT_n DDR0_ALERT_n DDR0_CAS_n DDR0_PAR DDR0_RAS_n DDR0_WE_n DDR0_A0 DDR0_A1 DDR0_A2 DDR0_A3 DDR0_A4 DDR0_A5 DDR0_A6 DDR0_A7 DDR0_A8 DDR0_A9 DDR0_A10 DDR0_A11 DDR0_A12 DDR0_A13 DDR0_BA0 DDR0_BA1 DDR0_BG0 DDR0_BG1 DDR0_CAL0 DDR0_CK0 DDR0_CK0_n DDR0_CKE0 DDR0_CKE1 DDR0_CS0_n DDR0_CS1_n DDR0_DM0 DDR0_DM1 DDR0_DQ0 DDR0_DQ1 DDR0_DQ2 DDR0_DQ3 DDR0_DQ4 DDR0_DQ5 DDR0_DQ6 DDR0_DQ7 DDR0_DQ8 DDR0_DQ9 DDR0_DQ10 DDR0_DQ11 DDR0_DQ12 DDR0_DQ13 DDR0_DQ14 DDR0_DQ15 DDR0_DQS0 DDR0_DQS0_n DDR0_DQS1 DDR0_DQS1_n DDR0_ODT0 DDR0_ODT1 DDR0_RESET0_n If DDRSS is not used, leave unconnected. Note: The DDR0 pins in this list can only be left unconnected when VDDS_DDR and VDDS_DDR_C are connected to VSS. The DDR0 pins must be connected as defined in the DDR Board Design and Layout Guidelines, when VDDS_DDR and VDDS_DDR_C are connected to a power source. W12 Y11 Y13 P11 R11 R10 VDDA_CORE_USB VDDA_1P8_USB VDDA_3P3_USB USB0 and USB1 share these power rails, so each of these balls must be connected to valid power sources when either USB0 or USB1 is used. If USB0 and USB1 are not used, each of these balls must be connected directly to VSS. www.ti.com AM625, AM625-Q1, AM623, AM620-Q1 SPRSP58B – JUNE 2022 – REVISED JUNE 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 85 Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1 |
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