TMPR4925 datasheet(378/590 Pages) TOSHIBA

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Chapter 11 Serial I/O Port

11-14

11.4.2

DMA/Interrupt Control Register 0 (SIDICR0)

0xF304 (Ch. 0)

DMA/Interrupt Control Register 1 (SIDICR1)

0xF404 (Ch. 1)

These registers use either DMA or interrupts to execute the Host Interface.

: Type

: Initial value

TDE

RDE

TIE

RIE

SPIE

CTSAC

STIE

R/W

: Type

000000

: Initial value

Bits

Mnemonic

Field Name

Description

31:16



Reserved



TDE

Transmit DMA

Transfer Enable

Transmit DMA Enable (Initial value: 0, R/W)

This field sets whether to use DMA in the method for writing transmission data to

the Transmit FIFO.

0: Do not use DMA.

1: Use DMA.

RDE

Receive DMA

Transfer Enable

Receive DMA Enable (Initial value: 0, R/W)

This field sets whether to use DMA in the method for reading reception data from

the Receive FIFO.

0: Do not use DMA.

1: Use DMA.

TIE

Transmit Data

Empty Interrupt

Enable

Transmit Data Empty Interrupt Enable (Initial value: 0, R/W)

When there is open space in the Transmit FIFO, this field sets whether to signal an

interrupt. Set “0” when in the DMA Transmit mode (TDE = 1).

0: Do not signal an interrupt when there is open space in the Transmit FIFO.

1: Signal an interrupt when there is open space in the Transmit FIFO.

RIE

Reception Data

Full Interrupt

Enable

Receive Data Full Interrupt Enable (Initial value: 0, R/W)

This field sets whether to signal interrupts when reception data is full

(SIDISRn.RDIS = 1) or a reception time out (SIDISRn.TOUT = 1) occurs. Set to “0”

when in the DMA Receive mode (RDE = 1).

0: Do not signal interrupts when reception data is full/reception time out occurred.

1: Signal interrupts when reception data is full/reception time out occurred.

SPIE

Reception Error

Interrupt Enable

Receive Data Error Interrupt Enable (Initial value: 0, R/W)

This field sets whether to signal interrupts when a reception error (Frame Error,

Parity Error, Overrun Error) occurs (SIDISR.ERI = 1).

0: Do not signal reception error interrupts.

1: Signal reception error interrupts.

10:9

CTSAC

CTSS Active

Condition

CTSS Active Condition (Initial value: 00, R/W)

This field specifies status change interrupt request conditions using the CTS Status

(CTSS) of the Status Change Interrupt Status Register.

00: Do not detect CTS signal changes.

01: Rising edge of the CTS pin

10: Falling edge of the CTS pin

11: Both edges of the CTS pin

8:6



Reserved



Figure 11.4.2 DMA/Interrupt Control Register (1/2)

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