TMPR4925 datasheet(382/590 Pages) TOSHIBA

382 / 590 page

Chapter 11 Serial I/O Port

11-18

11.4.4

Status Change Interrupt Status Register 0 (SISCISR0)

0xF30C (Ch. 0)

Status Change Interrupt Status Register 1 (SISCISR1)

0xF40C (Ch. 1)

: Type

: Initial value

5432

0OERS CTSS RBRKD TRDY TXALS UBRKD

R/W0C

RW0C : Type

0001

: Initial value

Bits

Mnemonic

Field Name

Description

31:6



Reserved



OERS

Overrun Error

Overrun Error Status (Initial value: 0, R/W0C)

This bit is immediately set to “1” when an overrun error is detected. This bit is cleared

when a “0” is written.

CTSS

CTS Status

CTS Terminal Status (Initial value: 0, R)

This field indicates the status of the CTS signal.

1: The CTS signal is High.

0: The CTS signal is Low.

RBRKD

Receiving Break

Receive Break (Initial value: 0, R)

This bit is set when a break is detected. This bit is automatically cleared when a

frame that is not a break is received.

1: Current status is Break.

0: Current status is not Break.

TRDY

Transmission

Data Empty

Transmit Ready (Initial value: 1, R)

This bit is set to “1” if at least one stage in the Transmit FIFO is free.

TXALS

Transmission

Complete

Transmit All Sent (Initial value: 1, R)

This bit is set to “1” if the Transmit FIFO and all transmission shift registers are

empty.

UBRKD

Break Detected

UART Break Detect (Initial value: 0, R/W0C)

This bit is set when a break is detected. Once set, this bit remains set until cleared by

writing a “0” to it.

Figure 11.4.4 Status Change Interrupt Status Register

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