TMPR4925 datasheet(431/590 Pages) TOSHIBA

431 / 590 page

Chapter 14 AC-link Controller

14-21

Bits

Mnemonic

Field Name

Description



Reserved



Disable Audio Receive-data DMA. (Initial value: –, W1C)

AUDIDMA

Disable Audio

Receive-data

DMA

W1C

0: No effect

1: Disables audio receive-data DMA.

Disable Audio LFE Transmit-data DMA. (Initial value: –, W1C)

LFEDMA

Disable Audio

LFE Transmit-

data DMA

W1C

0: No effect

1: Disables audio LFE transmit-data DMA.

Disable Audio Center Transmit-data DMA. (Initial value: –, W1C)

CENTDMA

Disable Audio

Center

Transmit-data

DMA

W1C

0: No effect

1: Disables audio Center transmit-data DMA.

Disable Audio Surround L&R Transmit-data DMA. (Initial value: –, W1C)

SURRDMA

Disable Audio

Surround L&R

Transmit-data

DMA

W1C

0: No effect

1: Disables audio Surround L&R transmit-data DMA.

Disable Audio PCM L&R Transmit-data DMA. (Initial value: –, W1C)

AUDODMA

Disable Audio

PCM L&R

Transmit-data

DMA

W1C

0: No effect

1: Disables audio PCM L&R transmit-data DMA.

7:5



Reserved



MIC Selection (Initial value: –, W1C)

MICSEL

MIC Selection

W1C

0: No effect

1: Selects PCM L&R (Slot 3&4) for audio reception

Deassert Warm Reset. (Initial value: –, W1C)

W1C

0: No effect

1: Deasserts warm reset.

WRESET

Deassert Warm

Reset

Note: The software must guarantee the warm reset assertion time meets the AC’97

specification (1.0

µs or more).

Disable Wake-up. (Initial value: –, W1C)

WAKEUP

Disable Wake-

up.

W1C

0: No effect

1: Disables wake-up from low-power mode.

Disable AC-link Low-power Mode. (Initial value: –, W1C)

LOWPWR

Disable AC-link

Low-power

Mode.

W1C

0: No effect

1: Releases SYNC and SDOUT signals from low.

Disable AC-link. (Initial value: –, W1C)

W1C

0: No effect

1: Asserts the ACRESET* signal to AC-link.

ENLINK

Disable AC-link

Note: The software must guarantee the ACRESET* signal assertion time meets the AC’97

specification (1.0

µs or more).

Figure 14.4.2 ACCTLDIS Register (2/2)

Clear xxxxDMA bits in ACCTLEN to “0” by using this register to disable transmit/receive-data

DMA and to stop transmission/reception by the AC-link. Note that if these bits are cleared while

output-slot data is flowing in the FIFO, ACLC may output a wrong data as the last sample. This

behavior will not occur if the software waits for data-flow completion by detecting underrun before it

disables the corresponding slot.

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