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TMPR4925 Datasheet(PDF) 441 Page - Toshiba Semiconductor |
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TMPR4925 Datasheet(HTML) 441 Page - Toshiba Semiconductor |
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441 / 590 page  Chapter 14 AC-link Controller 14-31 14.4.12 ACLC Slot Disable Register (ACSLTDIS) 0xF74C This register disables independently the AC-link slot data streams. 31 16 Reserved : Type : Initial value 15 10 9 8 7 6543 21 0 Reserved GPISLT GPOSLT MODI SLT MODO SLT Reserved AUDI SLT LFESLT CENT SLT SURR SLT AUDO SLT W1C W1C W1C W1C W1C W1C W1C W1C W1C : Type : Initial value Bits Mnemonic Field Name Description 31:10 Reserved — Disable GPI slot reception. (Initial value: –, W1C) 9 GPISLT Disable GPI slot reception W1C 0: No effect 1: Disables GPI slot reception. Disable GPO Slot transmission. (Initial value: –, W1C) 8 GPOSLT Disable GPO Slot transmission W1C 0: No effect 1: Disables GPO slot transmission. Disable Modem slot reception. (Initial value: –, W1C) 7MODISLT Disable Modem slot reception W1C 0: No effect 1: Disables modem slot reception. Disable Modem slot transmission. (Initial value: –, W1C) 6 MODOSLT Disable Modem slot transmission W1C 0: No effect 1: Disables modem slot transmission. 5 Reserved — Disable Audio slot reception. (Initial value: –, W1C) 4AUDISLT Disable Audio slot reception W1C 0: No effect 1: Disables audio slot reception. Disable Audio LFE slot transmission. (Initial value: –, W1C) 3LFESLT Disable Audio LFE slot transmission W1C 0: No effect 1: Disables audio LFE slot transmission. Disable Audio Center slot transmission. (Initial value: –, W1C) 2CENTSLT Disable Audio Center slot transmission W1C 0: No effect 1: Disables audio Center slot transmission. Disable Audio Surround L&R slot transmission. (Initial value: –, W1C) 1 SURRSLT Disable Audio Surround L&R slot transmission W1C 0: No effect 1: Disables audio Surround L&R slot transmission. Disable Audio PCM L&R slot transmission. (Initial value: –, W1C) 0AUDOSLT Disable Audio PCM L&R slot transmission W1C 0: No effect 1: Disables audio PCM L&R slot transmission. Figure 14.4.9 ACSLTDIS Register Writing a value into this register needs several BITCLK cycles to take effect. The software must guarantee that no write access be executed until the previous write access takes effect (completes), by reading the ACSLTEN.WRPEND bit prior to writing this register. If it is set for a long time, the BITCLK signal on the AC-link is probably inactive for whatever reason. |
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