TMPR4925 datasheet(461/590 Pages) TOSHIBA

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Chapter 15 Interrupt Controller

15-11

Bits

Mnemonic

Field Name

Explanation

17:16

IC16

Interrupt Source

Control 16

Interrupt Source Control 16 (Initial value: 00, R/W)

These bits specify the active state of DMA[2] interrupts.

00: Low level active

01: Disable

10: Disable

11: Disable

15:14

IC7

Interrupt Source

Control 7

Interrupt Source Control 7 (Initial value: 00, R/W)

These bits specify the active state of external INT[5] interrupts.

00: Low level active

01: High level active

10: Falling edge active

11: Rising edge active

13:12

IC6

Interrupt Source

Control 6

Interrupt Source Control 6 (Initial value: 00, R/W)

These bits specify the active state of external INT[4] interrupts.

00: Low level active

01: High level active

10: Falling edge active

11: Rising edge active

11:10

IC5

Interrupt Source

Control 5

Interrupt Source Control 5 (Initial value: 00, R/W)

These bits specify the active state of external INT[3] interrupts.

00: Low level active

01: High level active

10: Falling edge active

11: Rising edge active

9:8

IC4

Interrupt Source

Control 4

Interrupt Source Control 4 (Initial value: 00, R/W)

These bits specify the active state of external INT[2] interrupts.

00: Low level active

01: High level active

10: Falling edge active

11: Rising edge active

7:6

IC3

Interrupt Source

Control 3

Interrupt Source Control 3 (Initial value: 00, R/W)

These bits specify the active state of external INT[1] interrupts.

00: Low level active

01: High level active

10: Falling edge active

11: Rising edge active

5:4

IC2

Interrupt Source

Control 2

Interrupt Source Control 2 (Initial value: 00, R/W)

These bits specify the active state of external INT[0] interrupts.

00: Low level active

01: High level active

10: Falling edge active

11: Rising edge active

3:2

IC1

Interrupt Source

Control 1

Interrupt Source Control 1 (Initial value: 00, R/W)

These bits specify the active state of TX49 Write Timeout Error interrupts.

00: Low level active

01: Disable

10: Disable

11: Disable

1:0



Reserved



Figure 15.4.2 Interrupt Detection Mode Register 0 (2/2)

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