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TMPR4925 Datasheet(PDF) 460 Page - Toshiba Semiconductor |
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TMPR4925 Datasheet(HTML) 460 Page - Toshiba Semiconductor |
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460 / 590 page ![]() Chapter 15 Interrupt Controller 15-10 15.4.2 Interrupt Detection Mode Register 0 (IRDM0) 0xF604 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IC23 IC22 IC21 IC20 IC19 IC18 IC17 IC16 R/W R/W R/W R/W R/W R/W R/W R/W : Type 00 00 00 00 00 00 00 00 : Initial value 15 14 13 12 11 10 9 87654321 0 IC7 IC6 IC5 IC4 IC3 IC2 IC1 Reserved R/WR/W R/WR/W R/WR/W R/W : Type 00 00 00 00 00 00 00 : Initial value Bits Mnemonic Field Name Explanation 31:30 IC23 Interrupt Source Control 23 Interrupt Source Control 23 (Initial value: 00, R/W) These bits specify the active state of TMR[2] interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable 29:28 IC22 Interrupt Source Control 22 Interrupt Source Control 22 (Initial value: 00, R/W) These bits specify the active state of TMR[1] interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable 27:26 IC21 Interrupt Source Control 21 Interrupt Source Control 21 (Initial value: 00, R/W) These bits specify the active state of TMR[0] interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable 25:24 IC20 Interrupt Source Control 20 Interrupt Source Control 20 (Initial value: 00, R/W) These bits specify the active state of PCIC interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable 23:22 IC19 Interrupt Source Control 19 Interrupt Source Control 19 (Initial value: 00, R/W) These bits specify the active state of PDMAC interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable 21:20 IC18 Interrupt Source Control 18 Interrupt Source Control 18 (Initial value: 00, R/W) These bits specify the active state of IRC interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable 19:18 IC17 Interrupt Source Control 17 Interrupt Source Control 17 (Initial value: 00, R/W) These bits specify the active state of DMA[3] interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable Figure 15.4.2 Interrupt Detection Mode Register 0 (1/2) |
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