TMPR4925 datasheet(456/590 Pages) TOSHIBA

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Chapter 15 Interrupt Controller

15-6

Priorities are assigned as follows.

•

When interrupt levels differ, the interrupt with the higher interrupt level has priority (Table

15.3.2)

•

When multiple interrupts with the same interrupt level are simultaneously detected, the

interrupt with the smaller interrupt number has priority (Table 15.3.1).

In addition, the interrupt priority assignments are reevaluated under the following conditions. At this

time, the interrupt with the highest priority is selected and the Interrupt Factor field (CAUSE) and

Interrupt Level field (LVL) of the Interrupt Current Status Register (IRCS) are set again.

•

When an interrupt request with a higher interrupt level than that of the currently selected

interrupt is detected. However, when the interrupt levels are equal, the Interrupt Level field

(LVL) does not change even if the interrupt number is small.

•

When the interrupt level (IRLVLn.ILm) of the currently selected interrupt changes to a value

smaller than the current setting.

•

When the currently selected interrupt is cleared (refer to “15.3.6 Clearing Interrupt

Requests”).

15.3.5

Interrupt Notification

When the interrupt with the highest priority is selected, then the interrupt factor is reported to the

Interrupt Current Status Register (IRCS) and an interrupt is reported to the TX49/H2 core.

The TX49/H2 core distinguishes interrupt factors using the IP field (IP[7:2]) of the Cause Register.

The interrupt notification from the Interrupt Controller is reflected in the IP[2] bit. The Interrupt

Handler uses the IP[2] bit to judge whether or not there are interrupts from this Interrupt Controller and

uses the Interrupt Current Status Register (IRCS) to determine the interrupt cause.

The Interrupt Factor field (IRCS.CAUSE) value is reflected in the remaining bits of the IP field.

Since bit IP[7] is also being used for notification of TX49/H2 CPU core internal timer interrupts, the

contents specified by IP[7] differ according to whether internal timer interrupts are set to valid

(TINTDIS=0) or invalid (TINTDIS=1), as indicated Table 15.3.3.

The Interrupt Factor field (IRCS.CAUSE) value is reflected in the remaining bits of the IP field.

TINTDIS is the value that is set from ADDR[0] at the timing when the RESET* signal is deasserted.

See the explanation “3.3 Pin Multiplexing” for more information.

Table 15.3.3 Interrupt Notification to IP[7:2] of the CP0 Cause Register

TINTDIS

IP[7]

IP[6:3]

IP[2]

(Internal Timer Interrupts: Valid)

Internal Timer

Interrupt Notification

IRCS.CAUSE[3:0]

IRCS.IF

(Internal Timer Interrupts: Invalid)

IRCS.CAUSE[4:0]

IRCS.IF

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