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TMPR4925 Datasheet(PDF) 472 Page - Toshiba Semiconductor |
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TMPR4925 Datasheet(HTML) 472 Page - Toshiba Semiconductor |
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472 / 590 page  Chapter 15 Interrupt Controller 15-22 15.4.12 Interrupt Mask Level Register (IRMSK) 0xF640 31 16 Reserved : Type : Initial value 15 32 0 Reserved IML R/W : Type 000 : Initial value Bits Mnemonic Field Name Explanation 31:3 Reserved 2:0 IML Interrupt Mask Level Interrupt Mask Level (Initial value: 000, R/W) These bits specify the interrupt mask level. Masks interrupts with a mask level lower than the set mask level. 000: Interrupt mask level 0 (No interrupts masked) 001: Interrupt mask level 1 (Levels 2-7 enabled) 010: Interrupt mask level 2 (Levels 3-7 enabled) 011: Interrupt mask level 3 (Levels 4-7 enabled) 100: Interrupt mask level 4 (Levels 5-7 enabled) 101: Interrupt mask level 5 (Levels 6-7 enabled) 110: Interrupt mask level 6 (Level 7 enabled) 111: Interrupt mask level 7 (Interrupts disabled) Figure 15.4.12 Interrupt Mask Register |
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