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TMPR4925 Datasheet(PDF) 476 Page - Toshiba Semiconductor |
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TMPR4925 Datasheet(HTML) 476 Page - Toshiba Semiconductor |
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476 / 590 page ![]() Chapter 15 Interrupt Controller 15-26 Bits Mnemonic Field Name Explanation 5 IS5 Interrupt Status 5 IRINTREQ[5] status (Initial value: 0, R) This bit indicates the status of external INT[3] interrupts. 1: Interrupt requests 0: No interrupt requests 4 IS4 Interrupt Status 4 IRINTREQ[4] status (Initial value: 0, R) This bit indicates the status of external INT[2] interrupts. 1: Interrupt requests 0: No interrupt requests 3 IS3 Interrupt Status 3 IRINTREQ[3] status (Initial value: 0, R) This bit indicates the status of external INT[1] interrupts. 1: Interrupt requests 0: No interrupt requests 2 IS2 Interrupt Status 2 IRINTREQ[2] status (Initial value: 0, R) This bit indicates the status of external INT[0] interrupts. 1: Interrupt requests 0: No interrupt requests 1 IS1 Interrupt Status 1 IRINTREQ[1] status (Initial value: 0, R) This bit indicates the status of TX49 Write Timeout Error interrupts. 1: Interrupt requests 0: No interrupt requests 0 Reserved Figure 15.4.14 Interrupt Pending Status Register (3/3) |
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