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TMPR4925 Datasheet(PDF) 479 Page - Toshiba Semiconductor |
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TMPR4925 Datasheet(HTML) 479 Page - Toshiba Semiconductor |
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479 / 590 page  Chapter 15 Interrupt Controller 15-29 15.4.16 Interrupt Request Flag Register 0 (IRFLAG0) 0xF510 31 16 PF0 PF0 PF0 PF0 PF0 PF0 PF0 PF0 PF0 PF0 PF0 PF0 PF0 PF0 PF0 PF0 [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] R/W : Type 0x0000 : Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PF0 PF0 PF0 PF0 PF0 PF0 PF0 PF0 PF0 PF0 PF0 PF0 PF0 PF0 PF0 PF0 [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] R/W : Type 0x0000 : Initial value Bits Mnemonic Field Name Explanation 31:0 PF0[31:0] Flag 0 Interrupt Request Flag 0[31:0] (Initial value: 0x0000_0000, R/W) Changes made to this register are reflected in Flag Register 1 also since they are the same registers. Both “0” and “1” can be written to Flag Register 0. Figure 15.4.16 Interrupt Request Flag Register 0 15.4.17 Interrupt Request Flag Register 1 (IRFLAG1) 0xF514 31 16 PF1 PF1 PF1 PF1 PF1 PF1 PF1 PF1 PF1 PF1 PF1 PF1 PF1 PF1 PF1 PF1 [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] R/W : Type 0x0000 : Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PF1 PF1 PF1 PF1 PF1 PF1 PF1 PF1 PF1 PF1 PF1 PF1 PF1 PF1 PF1 PF1 [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] R/W : Type 0x0000 : Initial value Bits Mnemonic Field Name Explanation 31:0 PF1[31:0] Flag 1 Interrupt Request Flag 1[31:0] (Initial value: 0x0000_0000, R/W) Changes made to this register are reflected in Flag Register 0 also since they are the same registers. Writes to Flag Register 1 operate as follows: Write Write from the TX49/H2 core 1: Set the flag bit 0: No change Write from other devices (DMAC, PCIC) 1: Clear the flag bit 0: No change Read: Read the flag bit Figure 15.4.17 Interrupt Request Flag Register 1 |
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