TMPR4925 datasheet(478/590 Pages) TOSHIBA

478 / 590 page

Chapter 15 Interrupt Controller

15-28

Bits

Mnemonic

Field Name

Explanation

4:0

CAUSE

Interrupt Cause

Interrupt Cause (Initial value: 0x1F, R)

These bits specify the interrupt cause that was reported to the TX49/H2 core.

The values of these bits are undefined when there is no interrupt request.

00000: (Reserved)

00001: TX49 Write Timeout Error

00010: External INT[0] interrupt

00011: External INT[1] interrupt

00100: External INT[2] interrupt

00101: External INT[3] interrupt

00110: External INT[4] interrupt

00111: External INT[5] interrupt

01000: External INT[6] interrupt

01001: External INT[7] interrupt

01010: (Reserved)

01011: NAND Flash Controller interrupt

01100: SIO[0] interrupt

01101: SIO[1] interrupt

01110: DMA[0] interrupt

01111: DMA[1] interrupt

10000: DMA[2] interrupt

10001: DMA[3] interrupt

10010: IRC interrupt

10011: PDMAC interrupt

10100: PCIC interrupt

10101: TMR[0] interrupt

10110: TMR[1] interrupt

10111: TMR[2] interrupt

11000: SPI interrupt

11001: RTC interrupt

11010: ACLC interrupt

11011: ACLCPME interrupt

11100: CHI interrupt

11101: PCIERR interrupt

11110: PCIPME interrupt

11111: (Reserved)

Figure 15.4.15 Interrupt Current Status Register (2/2)

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