TMPR4925 datasheet(527/590 Pages) TOSHIBA

527 / 590 page

Chapter 17 Serial Peripheral Interface

17-11

Bits

Mnemonic

Field Name

Explanation

IFSPSE

Inter Frame

Space prescaler

enable

Inter Frame Space prescaler Enable (Initial value: 0, R/W)

Enable the Inter Frame Space prescaler.

0: Disable

1: Enable



Reserved



SBOS

SPI Bit Order

Select

SPI Bit Order Select (Initial value: 0, R/W)

Select bit order of transfer data.

0: LSB first operation, the least significant bit is shifted first.

1: MSB first operation, the most significant bit is shifted first.

SPOL

SPI Polarity

SPI clock Polarity (Initial value: 0, R/W)

Select the SPICLK polarity.

0: Active High Clocks selected; SPICLK idles low

1: Active Low Clocks selected; SPICLK idles high

SPHA

SPI Phase

SPI clock Phase (Initial value: 0, R/W)

Selects one of two fundamentally different transfer format.

0: Sampling on the first edge, Shift on the second edge.

1: Shift on the first edge, Sampling on the second edge.

Note 1: Bit 5 to Bit 0 could only be written, when the SPI module is in configuration mode.

Note 2: SPOL and SPHA bits determine the idle phase of SPICLK and the valid clock edge for sampling

data. Refer to “17.3.4 Transfer Format”.

Figure 17.4.2 SPI Control Register 0 (SPCR0) (2/2)

TMPR4925 Datasheet(PDF) 527 Page - Toshiba Semiconductor