TMPR4925 datasheet(528/590 Pages) TOSHIBA

528 / 590 page

Chapter 17 Serial Peripheral Interface

17-12

17.4.3

SPI Control Register 1 (SPCR1)

0xF808

Reserved

: Type

: Initial value

SER

Reserved

SSZ

R/W

: Type

0x00

00000

: Initial value

Bits

Mnemonic

Field Name

Explanation

31:16



Reserved



15:8

SER

SPI Data Rate

SPI Data Rate (Initial value: 0x00, R/W)

Control the bit-rate for the transmission.

The clock-rate on the SPI bus can be calculated using the following formula:

fBR = fSPI/2 (n + 1)

But n = 0 is not available.

Refer to Note 2.

7:5



Reserved



4:0

SSZ

SPI Transfer

Size

SPI Transfer size (Initial value: 00000b, R/W)

Select the number of bits to shift.

0x08: 8 bits

0x10: 16 bits

others: Reserved. Don’t set these values.

Note 1: This register could only be written, when the SPI module is in configuration mode.

Note 2: The SPICLK rate is shown in the table below in this time when MASTERCLK input is 40 MHz.

SER[7:0]

SPI Clock Rate

00000001b

10 MHz

00000010b

6.667 MHz

00000011b

5 MHz

00000100b

4 MHz

00000101b

3.33 MHz

…

00001001b

2 MHz

…

00010011b

1 MHz

…

11111111b

78.125 KHz

Figure 17.4.3 SPI Control Register 1 (SPCR1)

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