TMPR4925 datasheet(525/590 Pages) TOSHIBA

525 / 590 page

Chapter 17 Serial Peripheral Interface

17-9

17.4.1

SPI Master Control Register (SPMCR)

0xF800

Reserved

: Type

: Initial value

876

210

Reserved

OPMODE

Reserved

SPSTP

BCLR

R/W

R/C

: Type

: Initial value

Bits

Mnemonic

Field Name

Explanation

31 : 8



Reserved



7:6

OPMODE

Operation Mode

Operation Mode (Initial value: 01, R/W)

Set operation mode

00: Don’t care. Writing this value to the OPMODE bits doesn’t change any thing.

01: Configuration mode

10: Active mode (normal operation mode)

11: Reserved

5:3



Reserved





This bit is reserved. Don’t write “1” to this bit (Initial value: 0, R/W).

SPSTP

SPI Stop

SPI Stop (Initial value: 0, R/W)

If this flag is asserted, the module will stop the transferring after the current frame

has been completed. This bit could be set only when the SPI is in active mode.

Setting the SPI in configuration mode will clear this bit.

0: Normal operation

1: Stop after completion of the current transfer

BCLR

SPI Buffer Clear

SPI Buffer Clear (Initial value: 0, R/C)

This flag is used to clear the receive and transmit FIFO. The FIFO logic can be

reset by writing a “1” value to this bit. Please wait until the SPI module is idle

(SIDLE = 1) before activating the BCLR bit.

This register will always be read as “0”.

Write:

0: Don’t care

1: FIFO clear

Figure 17.4.1 SPI Master Control Register

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