TMPR4925 datasheet(521/590 Pages) TOSHIBA

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Chapter 17 Serial Peripheral Interface

17-5

17.3.4

Transfer Format

During a SPI transfer, data is simultaneously transmitted (shifted out serially) and received serially

(shifted in serially). The serial clock synchronizes shifting and sampling of the information on the two

serial data lines.

The transfer format depends on the setting of the SPHA and SPOL bits in the SPI Control Register 0

(SPCR0). SPHA switches between two fundamentally different protocols, which are described below.

17.3.4.1 SPHA Equals 0 Format

Figure 17.3.1 shows the transfer format for a SPHA=0 transfer.

Figure 17.3.1 Transfer format when SPHA is “0”.

In this transfer format, the bit value is captured on the first clock edge. This will be on a rising

edge when SPOL bit equals zero and on a falling edge when SPOL equals one. The value on the

SPIIN and SPIOUT signals changes with the second clock edge on SPICLK. This clock edge will

be a falling edge when SPOL equals zero and a rising edge, when SPOL equals one. With SPOL

equal to zero, the shift clock will be idle low. With SPOL equals 1 it will idle high.

SPICLK

(SPOL=0)

SPICLK

(SPOL=1)

SPIOUT

MSB

B6B5

B4B3B2

LSB

MSB

B6B5

B4B3B2

LSB

Sample Point

SPIIN

TMPR4925 Datasheet(PDF) 521 Page - Toshiba Semiconductor