TMPR4925 datasheet(522/590 Pages) TOSHIBA

522 / 590 page

Chapter 17 Serial Peripheral Interface

17-6

17.3.4.2 SPHA Equals 1 Format

Figure 17.3.2 shows the transfer format for a SPHA=1 transfer.

SPICLK

(SPOL=0)

SPICLK

(SPOL=1)

SPIIN

SPIOUT

MSB

LSB

MSB

LSB

Sample Point

Figure 17.3.2 Transfer format when SPHA is “1”.

In this transfer format, the value on the SPIIN and SPIOUT signals changes with the second

clock edge on SPICLK. This clock edge will be a rising edge when SPOL equals zero and a

falling edge, when SPOL equals one. The bit value is shifted in on the second clock edge. This

will be on a falling edge when SPOL bit equals zero and on a rising edge when SPOL equals one.

With SPOL equal to zero, the shift clock will be idle low. With SPOL equals 1 it will idle high.

17.3.5

Inter Frame Space Counter

Sometimes it is desirable to guarantee a minimum time between groups of data. The Inter Frame

Space Counter is used to provide delay between groups of data. If 16-bit data size is selected in the SPI

Control Register 1 (SPCR1), delay will be inserted after 16 bits of data are shifted. If 8-bit data size is

selected, delay will be inserted after 8 bits of data are shifted, as shown in Figure 17.4.3. Inter Frame

delay is added by setting the IFS[7:0] bits to a value other than 0. The number stored in these bits will

directly correspond to the number of the four times of SPI Master clock of delay that will be inserted

between frames. A zero value for these bits will imply seamless operation and the SPI will shift data

and provide clocks continuously as long as the software keeps up with the transmitter rate.

TMPR4925 Datasheet(PDF) 522 Page - Toshiba Semiconductor