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TMPR4925 Datasheet(PDF) 541 Page - Toshiba Semiconductor |
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TMPR4925 Datasheet(HTML) 541 Page - Toshiba Semiconductor |
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541 / 590 page  Chapter 18 NAND Flash Memory Controller 18-9 18.4.5 NAND Flash Memory Interrupt Mask Register (NDFIMR) 0xC010 31 16 Reserved : Type : Initial value 15 8 7 6 1 0 Reserved INTEN Reserved MRDY R/W R/W : Type 0 0 : Initial value Bits Mnemonic Field Name Description 31:8 Reserved 7 INTEN Interrupt Enable Interrupt Enable (Initial value: 0, R/W) Enable Interrupt. When this bit and MRDY bit in this register are set one and RDY bit in NDFISR becomes one, the interrupt occurs. 0: Disable 1: Enable 6:1 Reserved 0 MRDY Mask RDY interrupt Mask Ready Interrupt (Initial value: 0, R/W) This bit masks the RDY bit in NDFISR. If this bit one, RDY in NDFISR set when ND_RB* signal changes from Low to High. 0: Disable RDY in NDFISR 1: Enable RDY in NDFISR Figure 18.4.5 NAND Flash Memory Interrupt Mask Register (NDFIMR) |
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