TMPR4925 datasheet(538/590 Pages) TOSHIBA

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Chapter 18 NAND Flash Memory Controller

18-6

18.4.2

NAND Flash Memory Mode Control Register (NDFMCR)

0xC004

Reserved

: Type

: Initial value

Reserved

ECC

Reserved

BSPRT

ALE

CLE

R/W

R/W : Type

0000

: Initial value

Bits

Mnemonic

Field Name

Description

31:8



Reserved



Write Enable

Write Enable (Initial value: 0, R/W)

This bit enables the data write operation. When you write the data in the NAND

flash memory, this bit must be set one.

0: Inhibit write operation

1: Enable write operation

6:5

ECC

ECC Control

ECC Control 19 (Initial value: 00, R/W)

These bits control the ECC calculating circuits.

ECC

11: Reset ECC circuits.

00: ECC circuits is disable.

01: ECC circuits is enable.

10: Read ECC data calculated by NDFMC.

Chip Enable

Chip Enable (Initial value: 0, R/W)

Enable NAND Flash access. This bit must be set one when access to the NAND

Flash memory.

0: Disable (ND_CE* is high.)

1: Enable (ND_CE* is low.)



Reserved



BSPRT

Bus Separate

Bus Separate (Initial value: 0, R/W)

This bit enables the BUSSPRT* signal during NAND Flash memory access.

0: Disable

1: Enable

ALE

Address Latch

Enable

Address Latch Enable (Initial value: 0, R/W)

This bit specifies the value of ND_ALE signal.

0: Low

1: High

0CLE

Command Latch

Enable

Command Latch Enable (Initial value: 0, R/W)

This bit specifies the value of ND_CLE signal.

0: Low

1: High

Figure 18.4.2 NAND Flash Memory Mode Control Register (NDFMCR)

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