TMPR4925 datasheet(536/590 Pages) TOSHIBA

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Chapter 18 NAND Flash Memory Controller

18-4

(3) Read ECC data

•

NDFMCR (0xC004): Set 0x50 to do the ECC data read mode.

•

NDFDTR (0xC000):

Read 6 bytes ECC data.

First data:

LPR[7:0]

Second data:

LPR[15:8]

Third data:

CPR[5:0], 2’b11

Fourth data:

LPR[23:16]

Fifth data:

LPR[31:24]

Sixth data:

CPR[11:6], 2’b11

(4) Compare ECC data and run the error routine if error occurs by Software.

(5) Read other pages

•

NDFMCR (0xC004): Set 0x10.

•

NDFSR (0xC008):

Check BUSY flag. If it’s zero, go to the next. If it’s one, wait till

it will become zero.

•

Continue from (1) to (4) but (2-1) to (2-5) can be skipped when Sequential Read.

18.3.1.4 ID Read

The ID read sequence is below.

(1) NDFMCR (0xC004): Set 0x11 to assert ND_CLE* signal and do the command mode.

(2) NDFDTR (0xC000): Set 0x90 to write the ID Read command.

(3) NDFMCR (0xC004): Set 0x12 to assert ND_ALE* signal and do the address mode.

(4) NDFDTR (0xC000): Set 0x00.

(5) NDFMCR (0xC004): Set 0x10 to do the data mode without ECC calculation.

(6) NDFDTR (0xC000): Read Maker Code.

(7) NDFDTR (0xC000): Read Device Code.

18.3.2

ECC Control

NDFMC has the ECC calculating circuits. The circuits are controlled by NDFMCR. The Software

compares the ECC data and checks if error or not.

The calculated ECC data can be read from NDFDTR register when NDFMCR is 0xD0 (Write mode)

or 0x50 (Read mode). It is six bytes and six read operations for NDFDTR are needed. The order of the

data is following as.

First data:

LPR[7:0]

Second data: LPR[15:8]

Third data:

CPR[5:0], 2’b11

Fourth data:

LPR[23:16]

Fifth data:

LPR[31:24]

Sixth data:

CPR[11:6], 2’b11

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