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TMPR4925 Datasheet(PDF) 537 Page - Toshiba Semiconductor |
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TMPR4925 Datasheet(HTML) 537 Page - Toshiba Semiconductor |
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537 / 590 page ![]() Chapter 18 NAND Flash Memory Controller 18-5 18.4 Registers Table 18.4.1 NAND Flash Memory Control Registers Reference Address Bit Width Register Register Name 18.4.1 0xC000 32 NDFDTR NAND Flash memory Data transfer Register 18.4.2 0xC004 32 NDFMCR NAND Flash memory Mode Control Register 18.4.3 0xC008 32 NDFSR NAND Flash memory Status Register 18.4.4 0xC00C 32 NDFISR NAND Flash memory Interrupt Status Register 18.4.5 0xC010 32 NDFIMR NAND Flash memory Interrupt Mask Register 18.4.6 0xC014 32 NDFSPR NAND Flash memory Strobe pulse width Register 18.4.7 0xC018 32 NDFRSTR NAND Flash memory Reset Register 18.4.1 NAND Flash Memory Data Transfer Register (NDFDTR) 0xC000 31 16 Reserved : Type : Initial value 15 8 7 0 Reserved DATA R/W : Type : Initial value Bits Mnemonic Field Name Description 31:8 Reserved 7:0 DATA DATA Interrupt Detection Enable (Initial value: undefined, R/W) NAND Flash memory data. Read: The data is read from the NAND Flash memory. Note: Be able to read the data that was read from the NAND Flash memory at the previous read cycle for the NAND Flash memory. At the same time the NANDFC runs the next read cycle and stores the data in the buffer. Please take care to read the first byte data and the last byte data. Write: The data is written to the NAND Flash memory. Figure 18.4.1 NAND Flash Memory Data Transfer Register (NDFDTR) |
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