TMPR4925 datasheet(534/590 Pages) TOSHIBA

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Chapter 18 NAND Flash Memory Controller

18-2

18.3 Detailed Explanation

18.3.1

Access to NAND Flash Memory

The TX4925 NDFMC supports the interface between the NAND Flash Memory using register

indirect sequence. It has the ECC calculating circuits. Please see 18.3.2 in detail of the ECC. This

section describes the procedure to access to NAND Flash Memory.

Basically, set the command in NDFMCR at first and then read or write in NDFDTR. The read cycle

for NDFDTR is finished after the external read cycle for the NAND Flash Memory is finished. Equally,

the write cycle for NDFDTR is finished after the external write cycle for the NAND Flash Memory is

finished.

18.3.1.1 Initialize

The initialize sequence is below.

(1) NDFSPR (0xC014): Set the Low pulse width.

(2) NDFIMR (0xC010): Set 0x81 if need enable interrupt.

18.3.1.2 Write

The write sequence is below.

(1) NDFMCR (0xC004):

Set 0x70 to reset ECC data.

(2) NDFMC hasn’t WP* signal. It must be high using other logic for example PIO.

(3) Write 512 bytes

•

NDFMCR (0xC004): Set 0x91 to assert ND_CLE* signal and do the command mode.

•

NDFDTR (0xC000): Set 0x80 to write the Serial Data Input command.

•

NDFMCR (0xC004): Set 0x92 to assert ND_ALE* signal and do the address mode.

•

NDFDTR (0xC000): Set A[7:0], A[16:9], and A[24:17]. If need, set A[25].

•

NDFMCR (0xC004): Set 0xb0 to do the data mode.

•

NDFDTR (0xC000): Write 512 bytes data.

(4) Read ECC data

•

NDFMCR (0xC004): Set 0xd0 to do the ECC data read mode.

•

NDFDTR (0xC000): Read 6 bytes ECC data.

First data:

LPR[7:0]

Second data:

LPR[15:8]

Third data:

CPR[5:0], 2’b11

Fourth data:

LPR[23:16]

Fifth data:

LPR[31:24]

Sixth data:

CPR[11:6], 2’b11

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