TMPR4925 datasheet(535/590 Pages) TOSHIBA

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Chapter 18 NAND Flash Memory Controller

18-3

(5) Write 16 bytes redundant data

•

NDFMCR (0xC004): Set 0x90 to do the data mode without ECC.

•

NDFDTR (0xC000): Write 16 bytes redundant data.

D520: LPR[23:16]

D521: LPR[31:24]

D522: CPR[11:6], 2’b11

D525: LPR[7:0]

D526: LPR[15:8]

D527: CPR[5:0], 2’b11

(6) Run Page Program

•

NDFMCR (0xC004): Set 0x91 to assert ND_CLE* signal and do the command mode.

•

NDFDTR (0xC000): Set 0x10 to write the Page Program command.

•

NDFMCR (0xC004): Set 0x10 to deassert ND_ALE* signal.

•

NDFSR (0xC008):

Check BUSY flag. If it’s zero, go to the next. If it’s one, wait till

it will become zero.

(7) Read Status

•

NDFMCR (0xC004): Set 0x11 to assert ND_CLE* signal and do the command mode.

•

NDFDTR (0xC000): Set 0x70 to write the Read Status command.

•

NDFMCR (0xC004): Set 0x10 to deassert ND_CLE* signal.

•

NDFDTR (0xC000): Read the Status data from the NAND Flash memory.

(8) Continue from (1) to (7) for all other pages if need.

18.3.1.3 Read

The read sequence is below.

(1) NDFMCR (0xC004):

Set 0x70 to reset ECC data.

(2) Read 512 bytes

•

NDFMCR (0xC004): Set 0x11 to assert ND_CLE* signal and do the command mode.

(2-1)

•

NDFDTR (0xC000):

Set 0x00 to write the Read command. (2-2)

•

NDFMCR (0xC004): Set 0x12 to assert ND_ALE* signal and do the address mode.

(2-3)

•

NDFDTR (0xC000):

Set A[7:0], A[16:9], and A[24:17]. If need, set A[25]. (2-4)

•

NDFMCR (0xC004): Set 0x10 to deassert ND_ALE* signal. (2-5)

•

NDFSR (0xC008):

Check BUSY flag. If it’s zero, go to the next. If it’s one, wait till

it will become zero. (2-6)

•

NDFMCR (0xC004): Set 0x30 to do the data mode with ECC calculation. (2-7)

•

NDFDTR (0xC000):

Read 512 bytes data. (2-8)

•

NDFMCR (0xC004): Set 0x10 to do the data mode without ECC calculation. (2-9)

•

NDFDTR (0xC000):

Read 16 bytes redundant data. (2-10)

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