TMPR4925 datasheet(553/590 Pages) TOSHIBA

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Chapter 19 Real Time Clock (RTC)

19-5

19.4.3

Alarm Register (High) (ALARMHI)

0xF908

Reserved

: Type

: Initial value

Reserved

ALARMHI

R/W

: Type

0x000

: Initial value

Bits

Mnemonic

Field Name

Explanation

31:12



Reserved



11:0

ALARMHI

Alarm Register

(High)

Alarm Register (High) (Initial value: 0x000, R/W)

These bits provide the status of the bit 43 to 32 of Alarm counter.

Whenever the RTC counter reaches a count that is equal to the value of join to

these bits to Alarm Register (Low), the ALARMINT interrupt will be set.

Figure 19.4.3 Alarm Register (High) (ALARMHI)

19.4.4

Alarm Register (Low) (ALARMLO)

0xF90C

ALARMLO

R/W

: Type

0x0000

: Initial value

ALARMLO

R/W

: Type

0x0000

: Initial value

Bits

Mnemonic

Field Name

Explanation

31:0

ALARMLO

Alarm Register

(Low)

Alarm Register (Low) (Initial value: 0x0000_0000, R/W)

These bits provide the status of the bit 31 to 0 of Alarm counter.

Whenever the RTC counter reaches a count that is equal to the value of join to

Alarm Register (High) to these bits, the ALARMINT interrupt will be set.

Figure 19.4.4 Alarm Register (Low) (ALARMLO)

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