TMPR4925 datasheet(561/590 Pages) TOSHIBA

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Chapter 21 Extended EJTAG Interface

21-3

21.2.2

Instruction Register

The JTAG Instruction Register consists of an 8-bit shift register. This register is used for selecting

either one or both of the test to be performed and the Test Data Register to be accessed. The Data

RISC TX49/H2 Core Architecture” for more information regarding each instruction.

Table 21.2.1 Bit Configuration of JTAG Instruction Register

Instruction Code

MSB

→ LSB

Instruction

Selected Data Register

00000000 (0x00)

EXTEST

Boundary Scan Register

00000001 (0x01)

SAMPLE/PRELOAD

Boundary Scan Register

00000010 (0x02)

Reserved

00000011 (0x03)

IDCODE

Device ID Register

00000100 - 00001111

Reserved

00010000 (0x10)

HIGHZ

Bypass Register

00010001 - 01111111

Reserved

10000000 - 11111110

Refer to the TX49/H2 Core Architecture Manual

11111111 (0xFF)

BYPASS

Bypass Register

Figure 21.2.1 shows the format of the Instruction Register.

MSB

LSB

Figure 21.2.1 Instruction Register

The instruction code is shifted to the Instruction Register starting from the Least Significant Bit.

LSB

TDO

TDI

MSB

Figure 21.2.2 Shift Direction of the Instruction Register

21.2.3

Boundary Scan Register

The Boundary Scan Register contains a single 178-bit shift register to which all TX4925 I/O signals

except for power supply, TDI, TCK, TDO, TMS, TRST* are connected. TEST* and SCANENB*

cannot be tested, but it is possible for the Shift Register to sample the input. Figure 21.2.3. shows the

bits of the Boundary Scan Register.

255

Refer to Table 21.2.2.

Figure 21.2.3 Boundary Scan Register

Table 21.2.2 shows the scan sequence of 178 signals starting from TDI and ending with TDO.

TDI input is fetched to the Least Significant Bit (LSB) of the Boundary Scan Register and the Most

Significant Bit (MSB) of the Boundary Scan Register is sent from the TDO output.

Table 21.2.2 shows the boundary scan sequence relative to the processor signals.

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