ZL40294

DS20006768B-page 18

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2023 Microchip Technology Inc.

Both the SBI and the traditional interface feed common output enable/disable synchronization logic ensuring glitch free

enable and disable outputs, regardless of the method used.

Both interfaces are not active at the same time, and the SBEN pin selects which interface is active. Tying the SBEN high

enables the SBI. Tying the SBEN pin low enables the traditional OE# pin/SMBus output-enable interface.

When the SBI is enabled, OE[7:9, 11,12]# are disabled and vDATA, vCLK and vSHFT_LD# are enabled on vOE5#,

vOE6# and vOE10# respectively. Additionally, SMBus registers for masking off the disable function of the shift register

(0 value of a bit) become active.

When set to 1, the mask register forces its respective output to ‘enabled.’ This prevents accidentally disabling critical

outputs when using the SBI.

A SMBus read-back bit in Byte 4 indicates which output-enable control interface is enabled.

When the SBI is enabled and power has been applied, the SBI is active, even if the PWRGD/PWRDN# pin indicates

the part is in powerdown. This allows loading the shift register and transferring the contents to the output register before

the assertion of PWRGD.

Note that the mask registers are part of the normal SMBus interface and cannot be accessed when the PWRGD/

PWRDN# is low. Figure 3-13 provides a functional description of the SBI.

The SBI and the traditional SMBus output-enable registers both default to the ‘output enabled’ state at power-up. The

mask registers default to zero at power-up, allowing the shift register bits to disable their respective output.

FIGURE 3-13:

SIDE-BAND INTERFACE CONTROL LOGIC (FUNCTIONAL DESCRIPTION).

Figure 3-14 shows the basic timing of the side-band interface. The vSHFT_LD# pin goes high to enable the CLK input.

Next, the rising edge of CLK clocks enable vDATA into the shift register. After the 20th clock cycle for output 19, it stops

the clock low and drive the vSHFT_LD# pin low. The falling edge of vSHFT_LD# clocks the shift register contents to the

output register, enabling or disabling the outputs. It always shifts 20 bits of data into the shift register to control the out-

puts.