ZL40294 datasheet(14/46 Pages) MICROCHIP

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ZL40294

DS20006768B-page 14



2023 Microchip Technology Inc.

3.8

PWRGD / PWRDN#

PWRGD is asserted high and de-asserted low. De-assertion of PWRGD (pulling the signal low) is equivalent to indicat-

ing a powerdown condition. PWRGD (assertion) is used by the ZL40294 to sample initial configurations such as SA

selections.

After PWRGD has been asserted high for the first time, the pin becomes a PWRDN# (Power Down) pin which is used

to disable (drive low/low) all clocks cleanly and instruct the device to invoke power savings mode. PWRDN# is a com-

pletely asynchronous active low input. When entering power savings mode, PWRDN# should be asserted low prior to

shutting off the input clock or power to ensure all clocks shut down in a glitch free manner. When PWRDN# is de-

asserted high, all clocks will start and stop without any abnormal behavior and will meet all AC and DC parameters.

The assertion and de-assertion of PWRDN# is asynchronous.

Disabling of the CK_IN input clock prior to assertion of PWRDN# is an undefined mode and not recommended. Oper-

ation in this mode may result in glitches.

3.9

PWRDN# Assertion

When PWRDN# is sampled low by two consecutive rising edges of CK#, all differential outputs will be disabled on the

next CK# high to low transition.

FIGURE 3-6:

PWRDN# ASSERTION

3.10 PWRGD Assertion

PWRGD to the clock buffer should not be asserted before VDD reaches VDD(MIN). Prior to VDD(MIN) it is recommended

to hold PWRGD low (less than 0.5 V).

TABLE 3-2:

PWRGD/PWRDN# FUNCTIONALITY

PWRGD/PWRDN#

CK#

Low

Normal

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