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2023 Microchip Technology Inc.

DS20006768B-page 11

ZL40294

3.0

FUNCTIONAL DESCRIPTION

The ZL40294 is an ultra-low additive jitter, low power 1 to 20 fanout buffer which is fully compliant with Intel DB2000QL

Standard.

The device operates from 3.3V+/-5% supply as per Intel spec. Its operation is guaranteed over the industrial tempera-

ture range -40°C to +85°C.

3.1

Clock Inputs

The following blocks diagram shows how to terminate different signals fed to the inputs of ZL40294 device.

The device input can be fed with transmission lines of any impedance. Examples below show only 50Ω single ended,

85Ω differential and 100Ω differential which are the most common ones in practice. Figure 3-1 and Figure 3-2 show how

to terminate the input when driven from a push-pull and traditional HCSL drivers respectively.

Figure 3-3 shows how to terminate a single ended output such as LVCMOS. This example assumes 50Ω transmission

line which is the most common for single ended CMOS signaling. Ideally, resistors R1 and R2 should be 100Ω each and

RO + RS should be 50Ω so that the transmission line is terminated at both ends with characteristic impedance.

If the driving strength of the output driver is not sufficient to drive low impedance, the value of series resistor RS should

be increased. This will reduce the voltage swing at the input but this should be fine as long as the input voltage swing

requirement is not violated (Figure 3-3). The source resistors of RS = 270Ω could be used for standard LVCMOS driver.

This will provide 516 mV of voltage swing for 3.3V LVCMOS driver with load current of (3.3V/2) *(1/(270Ω + 50Ω)) =

5.16 mA.

For optimum performance both differential input pins (_p and _n) need to be DC biased to the same voltage. Hence, the

ratio R1/R2 should be equal to the ratio R3/R4.

FIGURE 3-1:

INPUT DRIVEN BY A PUSH-PULL DIFFERENTIAL OUTPUT.

FIGURE 3-2:

INPUT DRIVEN BY AN HCSL OUTPUT.