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MPF42791 Datasheet(PDF) 33 Page - Monolithic Power Systems |
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MPF42791 Datasheet(HTML) 33 Page - Monolithic Power Systems |
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33 / 75 page ![]() MPF42791 – 2 TO 16 BATTERY PACK FG W/ R DETECTION AND THERMAL MODEL MPF42791 Rev. 1.0 MonolithicPower.com 33 9/19/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. RCXN_CELL16_ BKUP, 0x03DE These bits are the backup register for cell 1 ’s connection resistance state. This address is a R/W alias for the RCXN_CELL16 register. The fuel gauge must be in learning backup mode for this register to be written. For more details, see the FG_BKUP_ENABLE register on page 33 and the FG_BKUP_FLAG register on page 54. Writing to this backup register or any other cell RCXN register prepares the fuel gauge to use the values written in this register as a starting point for the RCXN learning. 16, [15:0] R/W 16-bit unsigned integer LSB = 0.1m Ω 0m Ω 0m Ω to 6553.5m Ω FG_BKUP_ ENABLE, 0x03F0 Enables learning backup mode. See the FG_BKUP_FLAG register on page 54 for more details. 1, [0] Write-only Control Enable = 1 Disable = 0 0 0 to 1 Fuel Gauge Output Name, Address Description Bit Length, Position Type Encoding Decoded Default Value Range IT_DONE_INTR, 0x0400 Signals an interrupt when an iteration has been completed. Setting this bit to 1 clears the interrupt. This interrupt bit is automatically cleared when a new iteration is requested. 1, [0] W1C/RO Boolean true/false 0 0 to 1 STATUS_INTR, 0x0400 Signals an interrupt when there is a change in the STATUS register. Setting this bit to 1 clears the interrupt. 1, [1] W1C/RO Boolean true/false 0 0 to 1 EMTY_LIM_ INTR, 0x0400 Signals an interrupt when there is a change in the EMPTY_LIM register, which indicates that the empty limiting factor has changed. Setting this bit to 1 clears the interrupt. 1, [2] W1C/RO Boolean true/false 0 0 to 1 FULL_LIM_ INTR, 0x0400 Signals an interrupt when there is a change in the FULL_LIM register, which indicates that the full limiting factor has changed. Setting this bit to 1 clears the interrupt. 1, [3] W1C/RO Boolean true/false 0 0 to 1 SOC_PACK_ RSLT_INTR, 0x0400 Signals an interrupt when there is a change in the SOC_PACK_RSLT register, which indicates that the pack SOC result has changed. Setting this bit to 1 clears the interrupt. 1, [4] W1C/RO Boolean true/false 0 0 to 1 OT_WARN_ INTR, 0x0400 Signals an interrupt when an over- temperature (OT) condition occurs; check the statuses of OT_ID, WARN_OTDIS, WARN_OTCHG_CC, and WARN_OTCHG_END for more details. Setting this bit to 1 clears the interrupt. 1, [5] W1C/RO Boolean true/false 0 0 to 1 IDIS_AVG_ INTR, 0x0400 Signals an interrupt when there is a change in the IDIS_AVG_LRN or IDIS_AVG_RSLT registers, which indicates a change for the average discharge current learning. Setting this bit to 1 clears the interrupt. 1, [6] W1C/RO Boolean true/false 0 0 to 1 IDIS_END_ INTR, 0x0400 Signals an interrupt when there is a change in the IDIS_END_LRN or IDIS_END_RSLT registers, which indicates a change for the discharge end current learning. Setting this bit to 1 clears the interrupt. 1, [7] W1C/RO Boolean true/false 0 0 to 1 |
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