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MPF42791 Datasheet(PDF) 57 Page - Monolithic Power Systems

Part # MPF42791
Description  2 to 16 Stacked Cells Battery Pack Fuel Gauge with Resistance Detection and Thermal Model
PDF  75 Pages
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Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MPF42791 Datasheet(HTML) 57 Page - Monolithic Power Systems

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MPF42791 – 2 TO 16 BATTERY PACK FG W/ R DETECTION AND THERMAL MODEL
MPF42791 Rev. 1.0
MonolithicPower.com
57
9/19/2022
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
SOC_PACK_
RSLT_INTR_
EN,
0x1080
Enables a SOC_PACK_RSLT_INTR (pack
SOC result changed) interrupt.
1, [4]
R/W
Control
Enable = 1
Disable = 0
1
0 to 1
OT_WARN_
INTR_EN,
0x1080
Enables an OT_WARN_INTR interrupt.
1, [5]
R/W
Control
Enable = 1
Disable = 0
1
0 to 1
IDIS_AVG_
INTR_EN,
0x1080
Enables
an
IDIS_AVG_INTR
(average
discharge current learning) interrupt.
1, [6]
R/W
Control
Enable = 1
Disable = 0
1
0 to 1
IDIS_END_
INTR_EN,
0x1080
Enables an IDIS_END_INTR (discharge
termination current learning) interrupt.
1, [7]
R/W
Control
Enable = 1
Disable = 0
1
0 to 1
ICHG_CC_
INTR_EN,
0x1080
Enables an ICHG_CC_INTR (charge CC
current learning) interrupt.
1, [8]
R/W
Control
Enable = 1
Disable = 0
1
0 to 1
ICHG_END_
INTR_EN,
0x1080
Enables
an
ICHG_END_INTR
(charge
termination current learning) interrupt.
1, [9]
R/W
Control
Enable = 1
Disable = 0
1
0 to 1
VCHG_CV_
INTR_EN,
0x1080
Enables a VCHG_CV_INTR (charge CV
learning) interrupt.
1, [10]
R/W
Control
Enable = 1
Disable = 0
1
0 to 1
SORESR_
CELLS_INTR_
EN,
0x1080
Enables an SORESR_CELLS_INTR (ESR
learning) interrupt.
1, [11]
R/W
Control
Enable = 1
Disable = 0
1
0 to 1
RCXN_CELLS_
INTR_EN,
0x1080
Enables
an
RCXN_CELLS_INTR
(cell
resistance learning) interrupt.
1, [12]
R/W
Control
Enable = 1
Disable = 0
1
0 to 1
HCONV_
INTR_EN,
0x1080
Enables an HCONV_INTR (heat transfer
coefficient learning) interrupt.
1, [13]
R/W
Control
Enable = 1
Disable = 0
1
0 to 1
SOH_CELLS_
INTR_EN,
0x1080
Enables an SOH_CELLS_INTR (cell SOH
learning) interrupt.
1, [14]
R/W
Control
Enable = 1
Disable = 0
1
0 to 1
PDIS_LIM_
INTR_EN,
0x1080
Enables
a
PDIS_LIM_INTR
(discharge
power limiting factor change) interrupt.
1, [16]
R/W
Control
Enable = 1
Disable = 0
1
0 to 1
PCHG_LIM_
INTR_EN,
0x1080
Enables a PCHG_LIM_INTR (charge power
limiting factor change) interrupt.
1, [17]
R/W
Control
Enable = 1
Disable = 0
1
0 to 1
VCELL_MAX,
0x10C0
Sets the maximum voltage accepted at the
cell level.
16, [15:0]
R/W
16-bit unsigned
integer
LSB = 0.1mV
4200mV
0mV to
6553.5mV
VCELL_MAX_
MRGN,
0x10C2
Sets the maximum cell voltage margin.
8, [7:0]
R/W
8-bit unsigned
integer
LSB = 0.5mV
5mV
0mV to
127.5mV
VCELL_MIN,
0x10C3
Sets the minimum voltage accepted at the
cell level.
16, [15:0]
R/W
16-bit unsigned
integer
LSB = 0.1mV
3000mV
0mV to
6553.5mV



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