MPF42791 datasheet(12/75 Pages) MPS

12 / 75 page

MPF42791 – 2 TO 16 BATTERY PACK FG W/ R DETECTION AND THERMAL MODEL

MPF42791 Rev. 1.0

MonolithicPower.com

9/19/2022

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

Table 1: LED State-of-Charge Indicator Map

Pack SOC

LED Status

SOC > 90%

90%

≥ SOC >

70%

Off

70%

≥ SOC >

50%

Off

50%

≥ SOC >

30%

Off

30%

≥ SOC >

10%

Off

10%

≥ SOC

Off

Manual LED Control

With manual LED control, the host manually

controls

each

LED

via

the

corresponding

LEDx_ON register.

I2C COMMUNICATION INTERFACE

The

MPF42791

has

two

I2C-compatible

interfaces.

The

primary

I2C

channel

communicates

with

the

host

MCU

which

extracts the data from the AFE. The secondary

I2C channel is designed to monitor the fuel

gauge status in real time and configure the fuel

gauge using the MPF4279x graphic user

interface (GUI). Note that write operations are

only accepted from one channel at a time (the

primary channel by default). To write to the fuel

gauge using the secondary I2C channel, the

CHSL pin must be pulled high; otherwise, write

operations from this channel are ignored.

The I2C is a bidirectional, two-wire serial

interface. Only two bus lines are required: a

serial data line (SDA) and a serial clock line

(SCL). The device can be considered a master

or a slave when performing data transfers. A

device that initiates a data transfer on the bus

and generates the clock signals to permit the

transfer is considered a master. Any device that

the master addresses is considered a slave.

Both MPF42791 I2C interfaces operate as slave

devices with a configurable address (0x08 by

default). They receive control inputs from the

master

device

and

ignore

general

call

addresses.

The I2C interface supports both standard mode

(up to 100kbits), and fast mode (up to 400kbits).

The SDA and SCL lines are bidirectional with

open drain outputs that should be connected to

the positive supply voltage via a current source

or pull-up resistor. When the bus is free, both

lines are high.

The data on the SDA line must be stable during

the high period of the clock. the high or low state

of the data line can only change when the clock

signal on the SCL line is low. Note that a single

clock pulse is generated for each data bit

transferred (see Figure 7).

Figure 7: Bit Transfer on the I2C Bus

All transactions must begin with a start (S)

command and can be terminated with a stop (P)

command. Start and stop commands are always

generated by the master. A start command is

defined by a high-to-low transition on the SDA

line while SCL is high (see Figure 8). A stop

command is defined by a low-to-high transition

on the SDA line while the SCL is high (see

Figure 8). The bus is considered busy after a

start command and free after a stop command.

Figure 8: I2C Start (S) and Stop (P) Commands

Every byte on the SDA line must be 8 bits long

and must be followed by an acknowledge bit

(ACK). Note that data is transferred with the

most significant bit (MSB) first.

A slave cannot receive or transmit a complete

byte of data while performing other tasks, but it

can hold the SCL line low to force the master into

a wait state (clock stretching). Then, when the

slave is ready, data transfer continues, and the

clock line (SCL) is released. Figure 9 shows a

complete data transfer.

The acknowledgement takes place after every

byte and allows the receiver to signal to the

transmitter that the byte was successfully

received. All clock pulses are generated by the

master, including the 9th clock pulse (ACK).

The transmitter releases the SDA line during the

ACK clock pulse so that the receiver pulls the

MPF42791 Datasheet(PDF) 12 Page - Monolithic Power Systems

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