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MPF42791 Datasheet(PDF) 34 Page - Monolithic Power Systems |
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MPF42791 Datasheet(HTML) 34 Page - Monolithic Power Systems |
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34 / 75 page  MPF42791 – 2 TO 16 BATTERY PACK FG W/ R DETECTION AND THERMAL MODEL MPF42791 Rev. 1.0 MonolithicPower.com 34 9/19/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2022 MPS. All Rights Reserved. ICHG_CC_ INTR, 0x0400 Signals an interrupt when there is a change in the ICHG_CC_LRN or ICHG_CC_RSLT registers, which indicates a change for the charge CC learning. Setting this bit to 1 clears the interrupt. 1, [8] W1C/RO Boolean true/false 0 0 to 1 ICHG_END_ INTR, 0x0400 Signals an interrupt when there is a change in the ICHG_END_LRN or ICHG_END_RSLT registers, which indicates a change for the charge end current learning. Setting this bit to 1 clears the interrupt. 1, [9] W1C/RO Boolean true/false 0 0 to 1 VCHG_CV_ INTR, 0x0400 Signals an interrupt when there is a change in the VCHG_CV_LRN or VCHG_CV_RSLT registers, which indicates a change for the charge CV learning. Setting this bit to 1 clears the interrupt. 1, [10] W1C/RO Boolean true/false 0 0 to 1 SORESR_ CELLS_INTR, 0x0400 Signals an interrupt when there is a change in the RESR_LRN_CELLx or RESR_RSLT_CELLx registers, which indicates a change for ESR learning. Setting this bit to 1 clears the interrupt. 1, [11] W1C/RO Boolean true/false 0 0 to 1 RCXN_CELL S_INTR, 0x0400 Signals an interrupt when there is a change in the RCXN_LRN_CELLx or RCXN_RSLT_CELLx registers, which indicates a change for the cells’ connection resistance learning. Setting this bit to 1 clears the interrupt. 1, [12] W1C/RO Boolean true/false 0 0 to 1 HCONV_ INTR, 0x0400 Signals an interrupt when there is a change in the HCONV_LRN or HCONV_RSLT registers, which indicates a change for the heat transfer coefficient learning. Setting this bit to 1 clears the interrupt. 1, [13] W1C/RO Boolean true/false 0 0 to 1 SOH_CELLS_ INTR, 0x0400 Signals an interrupt when there is a change in the SOH_LRN_CELLx or SOH_RSLT_CELLx registers, which indicates a change for the cell’s SOH learning. Setting this bit to 1 clears the interrupt. 1, [14] W1C/RO Boolean true/false 0 0 to 1 PDIS_LIM_ INTR, 0x0400 Signals an interrupt when there is a change in the PDIS_LIM register, which indicates a change for the discharge power limiting factor. Setting this bit to 1 clears the interrupt. 1, [16] W1C/RO Boolean true/false 0 0 to 1 PCHG_LIM_ INTR, 0x0400 Signals an interrupt when there is a change in the PCHG_LIM register, which indicates a change for the charge power limiting factor. Setting this bit to 1 clears the interrupt. 1, [17] W1C/RO Boolean true/false 0 0 to 1 STATUS, 0x0403 Indicates the pack’s current status. 0: Charge 1: Discharge 2: Rest 2, [1:0] Read-only 8-bit unsigned integer LSB = 1 0 0 to 2 SOC_ABS_ CELL1, 0x0524 Returns cell 1 ’s absolute SOC. Shows as reserved. 8, [7:0] Read-only 8-bit unsigned integer LSB = 0.4% 0% 0% to 100% SOC_ABS_ CELL2, 0x0525 Returns cell 2’s absolute SOC. Shows as reserved. 8, [7:0] Read-only 8-bit unsigned integer LSB = 0.4% 0% 0% to 100% SOC_ABS_ CELL3, 0x0526 Returns cell 3’s absolute SOC. Shows as reserved. 8, [7:0] Read-only 8-bit unsigned integer LSB = 0.4% 0% 0% to 100% SOC_ABS_ CELL4, 0x0527 Returns cell 4’s absolute SOC. Shows as reserved. 8, [7:0] Read-only 8-bit unsigned integer LSB = 0.4% 0% 0% to 100% |
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