80221 datasheet(20/91 Pages) LSI

20 / 91 page

80220/80221

MD400159/E

3.9.7 Receive Activity Indication

Receive activity can be programmed to appear on some of

the PLED[5:0] pins by appropriately setting the program-

mable LED output select bits in the MI serial port LED

Configuration 2 register as shown in Table 5. When one

or more of the PLED[5:0] pins is programmed to be an

receive activity or activity detect output, that pin is asserted

low for 100 mS every time a receive packet occurs. The

PLED[5:0] outputs are open drain with pullup resistor and

can drive an LED from VCC or can drive another digital

input.

3.10 COLLISION

3.10.1 100 Mbps

Collision occurs whenever transmit and receive occur

simultaneously while the device is in Half Duplex.

Collision is sensed whenever there is simultaneous trans-

mission (packet transmission on TPO

±) and reception

(non idle symbols detected on TP input). When collision is

detected, the COL output is asserted, TP data continues to

be transmitted on twisted pair outputs, TP data continues

to be received on twisted pair inputs, and internal CRS

loopback is disabled. Once collision starts, CRS is as-

serted and stays asserted until the receive and transmit

packets that caused the collision are terminated.

The collision function is disabled if the device is in the Full

Duplex mode, is in the Link Fail state, or if the device is in

the diagnostic loopback mode.

3.10.2 10 Mbps

Collision in 10 Mbps mode is identical to the 100 Mbps

mode except, (1) reception is determined by the 10 Mbps

squelch criteria, (2) RXD[3:0] outputs are forced to all 0's,

(3) collision is asserted when the SQE test is performed,

(4) collision is asserted when the jabber condition has

been detected.

3.10.3 Collision Test

The controller interface collision signal, COL, can be

tested by setting the collision test register bit in the MI serial

port Control register. When this bit is set, TX_EN is looped

back onto COL and the TP outputs are disabled.

3.10.4 Collision Indication

Collision can be programmed to appear on the PLED2 pin

by appropriately setting the programmable LED output

select bits in the MI serial port Configuration 2 register, as

shown in Table 5. When the PLED2 pin is programmed

to be a collision detect output, this pin is asserted low for

100 mS every time a collision occurs. The PLED2 output

is open drain with pullup resistor and can drive an LED

from VCC or can drive another digital input.

3.11 START OF PACKET

3.11.1 100 Mbps

Start of packet for 100 Mbps mode is indicated by a unique

Start of Stream Delimiter (referred to as SSD). The SSD

pattern consists of the two /J/K/ 5B symbols inserted at the

beginning of the packet in place of the first two preamble

symbols, as defined in IEEE 802.3 Clause 24 and shown

in Figure 2.

The transmit SSD is generated by the 4B5B encoder and

the /J/K/ symbols are inserted by the 4B4B encoder at the

beginning of the transmit data packet in place of the first

two 5B symbols of the preamble, as shown in Figure 2.

The receive pattern is detected by the 4B5B decoder by

examining groups of 10 consecutive code bits (two 5B

words) from the descrambler. Between packets, the re-

ceiver will be detecting the idle pattern, which is 5B /I/

symbols. While in the idle state, CRS and RX_DV are

deasserted.

If the receiver is in the idle state and 10 consecutive code

bits from the receiver consist of the /J/K/ symbols, the start

of packet is detected, data reception is begun, CRS and

RX_DV are asserted, and /5/5/ symbols are substituted in

place of the /J/K/ symbols.

If the receiver is in the idle state and 10 consecutive code

bits from the receiver consist of a pattern that is neither /I/

I/ nor /J/K/ symbols but contains at least 2 non contiguous

0's, then activity is detected but the start of packet is

considered to be faulty and a False Carrier Indication (also

referred to as bad SSD) is signalled to the controller

interface. When False Carrier is detected, then CRS is

asserted, RX_DV remains deasserted, RXD[3:0]=1110

while RX_ER is asserted, and the bad SSD bit is set in the

MI serial port Status Output register. Once a False Carrier

Event is detected, the idle pattern (two /I/I/ symbols) must

be detected before any new SSD's can be sensed.

If the receiver is in the idle state and 10 consecutive code

bits from the receiver consist of a pattern that is neither /I/

I/ nor /J/K/ symbols but does not contain at least 2 non-

contiguous 0's, the data is ignored and the receiver stays

in the idle state.

3.11.2 10 Mbps

Since the idle period in 10 Mbps mode is defined to be the

period when no data is present on the TP inputs, then the

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