80221 datasheet(45/91 Pages) LSI

45 / 91 page

80220/80221

4-45

MD400159/E

5.2 TP TRANSMIT INTERFACE

The interface between the TP outputs on TPO

± and the

twisted pair cable is typically transformer coupled and

terminated with the two resistors as shown in Figures 11-

13.

The transformer for the transmitter is recommended to

have a winding ration of 2:1 with a center tap on the 2x

winding tied to VCC, as shown in Figures 11-13. The

specifications for such a transformer are shown in Table

21. Sources for the transformer are listed in Table 22.

The transmit output needs to be terminated with two

external termination resistors in order to meet the output

impedance and return loss requirements of IEEE 802.3.

It is recommended that these two external resistors be

connected from VCC to each of the TPO

± outputs, and

their value should be chosen to provide the correct termi-

nation impedance when looking back through the trans-

former from the twisted pair cable, as shown in Figures 11-

13. The value of these two external termination resistors

depends on the type of cable driven by the device. Refer

to the Cable Selection section for more details on choosing

the value of these resistors.

To minimize common mode output noise and to aid in

meeting radiated emissions requirements, it may be nec-

essary to add a common mode choke on the transmit

outputs as well as add common mode bundle termination.

The qualified transformers

mentioned in Table 22 all

contain common mode chokes along with the transform-

ers on both the transmit and receive sides, as shown in

Figures 11-13. Common mode bundle termination may be

needed and can be achieved by tying the unused pairs in

the RJ45 to chassis ground through 75 Ohm resistors and

a 0.01 uF capacitor, as shown in Figures 11-13.

To minimize noise pickup into the transmit path in a system

or on a PCB, the loading on TPO

± should be minimized

and both outputs should always be loaded equally.

5.0 APPLICATION INFORMATION

5.1 EXAMPLE SCHEMATICS

A typical example schematic of the 80220/80221 used in

an adapter card application is shown in Figure 11, a hub

application is shown in Figure 12, and an external PHY

application is shown in Figure 13.

5.3 TP RECEIVE INTERFACE

Receive data is typically transformer coupled into the

receive inputs on TPI

± and terminated with

external

resistors as shown in Figures 11-13.

The transformer for the receiver is recommended to have

a winding ration of 1:1, as shown in Figures 11-13. The

specifications for such a transformer are shown in Table

21. Sources for the transformer are listed in Table 22.

The receive input needs to be terminated with the correct

termination impedance meet the input impedance and

return loss requirements of IEEE 802.3. In addition, the

receive TP inputs need to be attenuated. It is recom-

mended that both the termination and attenuation be

accomplished by placing four external resistors in series

across the TPI

± inputs as shown in Figures 11-13. The

resistors should be 15%/35%/35%/15% of the total series

resistance, and the total series resistance should be equal

to the characteristic impedance of the cable (100 Ohms for

UTP, 150 Ohms for STP). It is also recommended that a

0.01

µF capacitor be placed between the center of the

series resistor string and VCC in order to provide an AC

ground for attenuating common mode signal at the input.

This capacitor is also shown in Figures 11-13.

To minimize common mode input noise and to aid in

meeting susceptibility requirements, it may be necessary

to add a common mode choke on the receive input as well

as add common mode bundle termination. The qualified

transformers mentioned in Table 22 all contain common

mode chokes along with the transformers on both the

transmit and receive sides, as shown in Figures 11-13.

Common mode bundle termination may be needed and

can be achieved by tying the receive secondary center tap

and the unused pairs in the RJ45 to chassis ground

through 75 Ohm resistors and a 0.01

µF capacitor, as

shown in Figures 11-13.

In order to minimize noise pickup into the receive path in

a system or on a PCB,

loading on TPI

± should be

minimized and both inputs should be loaded equally.

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