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80221 Datasheet(PDF) 63 Page - LSI Computer Systems |
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80221 Datasheet(HTML) 63 Page - LSI Computer Systems |
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63 / 91 page ![]() 80220/80221 4-63 MD400159/E 63 RECEIVE TIMING CHARACTERISTICS Refer to Figures 19-23 for Timing Diagrams LIMIT SYM PARAMETER MIN TYP MAX UNIT CONDITIONS t 31 Start Of Packet To CRS 200 nS 100 Mbps, MII Assert Delay 200 nS 100 Mbps, FBI 700 nS 10 Mbps t 32 End Of Packet To CRS 130 240 nS 100 Mbps, MII Deassert Delay 240 nS 100 Mbps, FBI 600 nS 10 Mbps. Relative To Start Of SOI Pulse t 33 Start Of Packet To 240 nS 100 Mbps RX_DV Assert Delay 3600 nS 10 Mbps t 34 End Of Packet To 280 nS 100 Mbps RX_DV Deassert Delay 1000 nS 10 Mbps. Relative To Start Of SOI Pulse t 37 RX_CLK To RX_DV, -8 8 nS 100 Mbps RXD, RX_ER Delay -80 80 nS 10 Mbps t 38 RX_CLK High Time 18 20 22 nS 100 Mbps 180 200 600 nS 10 Mbps t 39 RX_CLK Low Time 18 20 22 nS 100 Mbps 180 200 600 nS 10 Mbps t 40 SOI Pulse Minimum 125 200 nS 10 Mbps Width Required for Idle Measure TPI ± from last zero cross Detection to 0.3V point. t 41 Receive Input Jitter ±3.0 nS pk - pk 100 Mbps ±13.5 nS pk -pk 10 Mbps t 43 PLEDn Delay Time 25 mS PLEDn Programmed for Activity t 44 PLEDn Pulse Width 80 105 mS PLEDn Programmed for Activity t 45 RX_CLK, RXD, CRC, 10 nS RX_DV, RX_ER Output Rise and Fall Times t 46 RX_EN Deassert to Rcv 40 nS MII Output HI-Z Delay t 47 RX_EN Assert to Rcv 40 nS MII Output Active Delay |
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