80221 datasheet(5/91 Pages) LSI

5 / 91 page

80220/80221

4-5

MD400159/E

Pin#

I/O

Description

44L 64L

VCC6

—

Positive Supply. 5

± 5% Volts

VCC5

VCC4

VCC3

VCC2

VCC1

GND6

—

Ground. 0 Volts

GND5

GND4

GND3

GND2

GND1

TPO+

Twisted Pair Transmit Output, Positive.

TPO -

Twisted Pair Transmit Output, Negative.

TPI+

Twisted Pair Receive Input, Positive.

TPI -

Twisted Pair Receive Input, Negative.

REXT

—

Transmit Current Set. An external resistor connected between this pin and GND will set the

output current level for the twisted pair outputs.

OSCIN

Clock Oscillator Input. There must be either a 25 Mhz crystal between this pin and GND or

a 25 Mhz clock applied to this pin. TX_CLK output is generated from this input.

TX_CLK

Transmit Clock Output. This controller interface output provides a clock to an external

controller. Transmit data from the controller on TXD, TX_EN, and TX_ER is clocked in on

rising edges of TX_CLK and OSCIN.

TX_EN

Transmit Enable Input. This controller interface input has to be asserted active high to

indicate that data on TXD and TX_ER is valid, and it is clocked in on rising edges of TX_CLK

and OSCIN.

TXD3

Transmit Data Input. These controller interface inputs contain input nibble data to be

TXD2

transmitted on the TP outputs, and they are clocked in on rising edges of TX_CLK and OSCIN

TXD1

when TX_EN is asserted.

TXD0

TX_ER /

Transmit Error Input. This controller interface input causes a special pattern to be

TXD4

transmitted on the twisted pair outputs in place of normal data, and it is clocked in on rising

edges of TX_CLK when TX_EN is asserted.

If the device is placed in the Bypass 4B5B Encoder mode, this pin is reconfigured to be the

fifth TXD transmit data input, TXD4.

RX_CLK

Receive Clock Output. This controller interface output provides a clock to an external

controller. Receive data on RXD, RX_DV, and RX_ER is clocked out on falling edges of

RX_CLK.

CRS

Carrier Sense Output. This controller interface output is asserted active high when valid data

is detected on the receive twisted pair inputs, and it is clocked out on falling edges of RX_CLK.

RX_DV

Receive Data Valid Output. This controller interface output is asserted active high when valid

decoded data is present on the RXD outputs, and it is clocked out on falling edges of RX_CLK.

RXD3

Receive Data Output. These controller interface outputs contain receive nibble data from

RXD2

the TP input, and they are clocked out on falling edges of RX_CLK.

RXD1

RXD0

Name

1.0 Pin Description

80221 Datasheet(PDF) 5 Page - LSI Computer Systems

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