80221 datasheet(30/91 Pages) LSI

30 / 91 page

80220/80221

MD400159/E

3.26.5 Frame Structure

The structure of the serial port frame is shown in Table 8

and a timing diagram of a frame is shown in Figure 9. Each

serial port access cycle consists of 32 bits (or 192 bits if

multiple

access

enabled

and

REGAD[4:0]=11111), exclusive of idle. The first 16 bits of

the serial port cycle are always write bits and are used for

addressing. The last 16/176 bits are from one/all of the

11 data registers.

The first 2 bits in Table 8 and Figure 9 are start bits and

need to be written as a 01 for the serial port cycle to

continue. The next 2 bits are a read and write bit which

determine if the accessed data register bits will be read or

write. The next 5 bits are device addresses and they must

match the inverted values latched in from pins MDA[4:0]

during the power-on reset time for the serial port access to

continue. The next 5 bits are register address select bits

which select one of the five data registers for access. The

next 1 bit is a turnaround bit which is not an actual register

bit but extra time to switch MDIO from write to read if

necessary, as shown in Figure 2. The final 16 bits of the

MI serial port cycle (or 176 bits if multiple register access

is enabled and REGAD[4:0]=11111) come from the spe-

cific data register designated by the register address bits

REGAD[4:0].

3.26.6 Register Structure

The 80220/80221 has eleven internal 16 bit registers. Ten

registers are available for setting configuration inputs and

reading status outputs, and one register is reserved for

factory use. A map of the registers is shown in Table 9.

The ten accessible registers consist of six registers that

are defined by IEEE 802.3 specifications (Registers 0-5)

and four registers that are unique to the 80220/80221

(Registers 16-19).

The structure and bit definition of the Control register is

shown in Table 10. This register stores various configura-

tion inputs and its bit definition complies with the IEEE

802.3 specifications.

The structure and bit definition of the Status register is

shown in Table 11. This register contains device capabili-

ties and status output information. and its bit definition

complies with the IEEE 802.3 specifications.

The structure and bit definition of the PHY ID #1 and #2

registers is shown in Tables 12 and 13, respectively.

These registers contain an identification code unique to

the 80220/80221 and their bit definition complies with the

IEEE 802.3 specifications.

The structure and bit definition of the AutoNegotiation

Advertisement and AutoNegotiation Remote End Capabil-

ity registers is shown in Tables 14 and 15, respectively.

These registers are used by the AutoNegotiation algorithm

and their bit definition complies with the IEEE 802.3

specifications.

The structure and bit definition of the Configuration 1 and

Configuration 2 registers is shown in Table 16 and 17,

respectively. These registers store various configuration

inputs.

The structure and bit definition of the Status Output regis-

ter is shown in Table 18. This register contains output

status information.

The structure and bit definition of the Mask register is

shown in Table 19. This register allows each R/LT bit in the

Status Output register to be masked out or removed as a

bit that will set interrupt.

be set to the defaults for normal operation.

3.26.7 Interrupt

The 80220/80221 has hardware and software interrupt

capability. The interrupt is triggered by certain output

status bits (also referred to as interrupt bits) in the serial

port. As indicated previously, R/LT bits are read bits that

latch on transition. R/LT bits are also interrupt bits if they

are not masked out with the Mask register bits. Interrupt

bits automatically latch themselves into their register loca-

tions and assert the interrupt indication when they change

state. Interrupt bits stay latched until they are read. When

interrupt bits are read, the interrupt indication is deasserted

and the interrupt bits that caused the interrupt to happen

are updated to their current value. Each interrupt bit can

be individually masked and subsequently be removed as

an interrupt bit by setting the appropriate mask register bits

in the Mask register.

Interrupt indication is done in three ways: (1) MDINT pin,

(2) INT bit in the MI serial port Status Output register, and

(3) interrupt pulse on MDIO. The MDINT pin is an active

low interrupt output indication. The INT bit is an active high

interrupt register bit that resides in the Status Output

The interrupt pulse on MDIO also indicates

interrupt and is available when the interrupt pulse select bit

is set in the MI serial port Configuration 2 register. When

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