TAS5028 datasheet(37/84 Pages) TI

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TAS5028 Controls and Status

SLES112 — June 2004

TAS5028

2.3.1 Channel Configuration Registers

In order for the TAS5028 to have full control of the power stages, registers 0x05 to 0x0C must be programmed

to reflect the proper power stage and how each one should be controlled. Channel configuration registers

consist of eight registers, one for each channel.

The primary reason for using these registers is that different power stages require different handling during

start up, mute/unmute, shutdown, and error recovery. The TAS5028 must select the sequence that gives the

best click and pop performance and insure that the bootstrap capacitor is charged correctly during start up.

This sequence depends on which power stage is present at the TAS5028 output.

Table 2 - 5. Description of the Channel Configuration Registers (0x05 to 0x0C)

BIT

DESCRIPTION

Enable/disable error recovery sequence. In case the BKND_RECOVERY pin is pulled low, this register determines if this channel is

to follow the error recovery sequence or to continue with no interruption.

Determines if the power stage needs the TAS5028 VALID pin to go low to reset the power stage. Some power stages can be reset

by a combination of PWM signals. For these devices, it is recommended to set this bit low, since the VALID pin is shared for power

stages. This provides better control of each power stage.

Determines if the power stage needs the TAS5028 VALID pin to go low to mute the power stage. Some power stages can be muted

by a combination of PWM signals. For these devices, it is recommended to set this bit low, since the VALID pin is shared for power

stages. This provides better control of each power stage.

Inverts the PWM output. Inverting the PWM output can be an advantage if the power stage input pin are opposite the TAS5028 PWM

pinout. This makes routing on the PCB easier. To keep the phase of the output the speaker terminals must also be inverted.

The power stage TAS5182 has a special PWM input. To ensure that the TAS5028 has full control in all occasions, the PWM output

must be remapped.

Can be used to handle click and pop for some applications.

This bit is normally used together with D2. For some power stages, both PWM signals must be high to get the desired operation of

both speaker outputs to be low. This bit sets the PWM outputs high-high during mute.

Not used

Table 2 - 6 lists the optimal setting for each output stage configuration. Note that the default value is applicable

in all configurations except the TAS5182 SE/BTL configuration.

Table 2 - 6. Recommended TAS5028 Configurations for Texas Instruments Power Stages

DEVICE

ERROR RECOVERY

CONFIGURATION

Default

RES

BTL

RES

BTL

TAS5111

RES

TAS5111

AUT

BTL

AUT

RES

BTL

TAS5112

RES

TAS5112

AUT

BTL

AUT

TAS5182

RES

BTL

TAS5182

RES

RES: The output stage requires VALID to go low to recover from a shutdown.

AUT: The power stage can auto recover from a shutdown.

BTL: Bridge tied load configuration

SE: Single-ended configuration

2.3.2 Headphone Configuration Registers

The headphone configuration controls are identical to the speaker configuration controls. The headphone

configuration control settings are used in place of the speaker configuration control settings for channels 1

and 2 when the headphones are selected. In reality however, there is only one used configuration setting for

headphones and that is the default setting.

TAS5028 Datasheet(PDF) 37 Page - Texas Instruments

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