TAS5028 datasheet(16/84 Pages) TI

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Introduction

SLES112 — June 2004

TAS5028

TERMINAL

DESCRIPTION

TERMIN-

ATION

5-V

TOLERANT

I/O

NO.

DESCRIPTION

TERMIN-

ATION

5-V

TOLERANT

I/O

NAME

MCLK

5 V

Pulldown

MCLK is a 3.3-V clock master clock input. The input frequency of this clock can

range from 4 MHz to 50 MHz.

RESERVED

Connect to digital ground

NOTES:

1. Type: A = analog; D = 3.3-V digital; P = power / ground / decoupling; I = input; O = output

2. All pullups are 200-

µA weak pullups and all pulldowns are 200-µA weak pull downs. The pullups and pulldowns are included to assure

proper input logic levels if the terminals are left unconnected (pullups => logic 1 input; pulldowns => logic 0 input). Devices that drive

inputs with pull ups must be able to sink 200

µA, while maintaining a logic 0 drive level. Devices that drive inputs with pulldowns must

be able to source 200

µA, while maintaining a logic ‘1’ drive level.

3. If desired, low ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling

capacitors of equal value provide an extended high frequency supply decoupling. This approach avoids the potential of producing

parallel resonance circuits that have been observed when paralleling capacitors of different values.

4. 13.5-MHz crystal (HCM49)

1.4

TAS5028 Functional Description

Figure 1 - 4 shows the TAS5028 functional structure. The next sections describe the TAS5028 functional

blocks:

•

Power Supply

•

Clock, PLL, and Serial Data Interface

•

Serial Control Interface

•

Device Control

•

Digital Audio Processor (DAP)

•

Pulse Width Modulation (PWM) Processor

1.4.1 Power Supply

The power supply section contains supply regulators that provide analog and digital regulated power for

various sections of the TAS5028. The analog supply supports the analog PLL, while digital supplies support

the digital PLL, the digital audio processor (DAP), the pulse width modulator (PWM), and the output control

(reclocker). The regulators can also be turned off when terminals RESET and PDN are both low.

1.4.2 Clock, PLL, and Serial Data Interface

The TAS5028 is a clock slave only device and it requires the use of an external 13.5 MHz crystal. It accepts

MCLK, SCLK, and LRCLK as inputs only.

The TAS5028 uses the external crystal to provide a time base for:

•

Continuous data and clock error detection and management

•

Automatic data rate detection and configuration

•

Automatic MCLK rate detection and configuration (automatic bank switching)

•

Supporting I2C operation/ communication while MCLK is absent

The TAS5028 automatically handles clock errors, data rate changes, and master clock frequency changes

without requiring intervention from an external system controller. This feature significantly reduces system

complexity and design.

TAS5028 Datasheet(PDF) 16 Page - Texas Instruments

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