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TAS5028 Datasheet(PDF) 71 Page - Texas Instruments |
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TAS5028 Datasheet(HTML) 71 Page - Texas Instruments |
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71 / 84 page ![]() Serial Control Interface Register Definitions 63 SLES112 — June 2004 TAS5028 6.16 Bass and Treble Bypass Register (0x89 – 0x90, Channels 1 - 8) Channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into registers 0x89, 0x8A, 0x8B, 0x8C,0x8D, 0x8E, 0x8F, and 0x90. Eight bytes are written for each channel. Each gain coefficient is in 28-bit (5.23) format so 0x800000 is a gain of 1. Each gain coefficient is written as a 32-bit word with the upper four bits not used. Table 6 - 17. Bass and Treble Bypass Register Format (0x89 - 0x90) REGISTER NAME TOTAL BYTES CONTENTS INITIALIZATION VALUE Channel bass and treble bypass 8 U 31:28), Bypass (27:24), Bypass (23:16), Bypass (15:8), Bypass (7:0) 0x00, 0x80, 0x00, 0x00 Channel bass and treble inline 8 U (31:28), Inline (27:24), Inline (23:16), Inline (15:8), Inline (7:0) 0x00, 0x00, 0x00, 0x00 6.17 8x2 Output Mixer Registers (0xAA – 0xAF) Output mixers for channels 1–6 map to registers 0xAA – 0xAF. Total data per register is 8 bytes. Table 6 - 18. Output Mixer Control Register Format (Upper 4 Bytes) D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION 0 0 0 0 Select channel 1 to output mixer 0 0 0 1 Select channel 2 to output mixer 0 0 1 0 Select channel 3 to output mixer 0 0 1 1 Select channel 4 to output mixer 0 1 0 0 Select channel 5 to output mixer 0 1 0 1 Select channel 6 to output mixer 0 1 1 0 Select channel 7 to output mixer 0 1 1 1 Select channel 8 to output mixer G27 G26 G25 G24 Selected channel gain (upper 4 bits) D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION G23 G22 G21 G20 G19 G18 G17 G16 Selected channel gain (continued) D15 D14 D13 D12 D11 D10 D9 D8 FUNCTION G15 G14 G13 G12 G11 G10 G9 G8 Selected channel gain (continued) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION G7 G6 G5 G4 G3 G2 G1 G0 Selected channel gain (lower 8 bits) |
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