TAS5028 datasheet(39/84 Pages) TI

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TAS5028 Controls and Status

SLES112 — June 2004

TAS5028

2.3.5 Volume and Mute Update Rate

The TAS5028 has fixed soft volume and mute ramp durations. The ramps are linear. The soft volume and mute

ramp rates are adjustable by programming the I2C register 0xD0 for the appropriate number of steps to be

512, 1024, or 2048. The update is performed at a fixed rate regardless of the sample rate.

•

In normal speed, the update rate is 1 step every 4 / Fs seconds.

•

In double speed, the update is 1 step every 8 / Fs seconds.

•

In quad speed, the update is 1 step every 16 / Fs seconds.

Because of processor loading, the update rate can increase for some increments by +1/Fs to +3/Fs. However,

the variance of the total time to go from +18 dB to mute is less than 25%.

Table 2 - 8. Volume Ramp Rates in ms

NUMBER OF STEPS

SAMPLE RATE (KHZ)

NUMBER OF STEPS

44.1, 88.2, 176.4

32, 48, 96, 192

512

46.44 ms

42.67 ms

1024

92.88 ms

85.33 ms

2048

185.76 ms

170.67 ms

2.3.6 Modulation Index Limit

PWM modulation is a linear function of the audio signal. When the audio signal is 0, the PWM modulation is

50%. When the audio signal increases towards full scale, the PWM modulation increases towards 100%. For

negative signals, the PWM modulations fall below 50% towards 0%.

However, there is a limit to the maximum modulation possible. During the off-time period, the power stage

connected to the TAS5028 output needs to get ready for he next on-time period. The maximum possible

modulation is then set by the power stage requirements. All Texas Instruments power stages needs maximum

modulation to be 97.7%. This is also the default setting of the TAS5028. Default settings can be changed in

the Modulation Index Register (0x16).

Note that no change should be made to this register when using Texas Instruments power stages.

2.3.7 Inter-channel Delay

An 8-bit value can be programmed to each of the eight PWM inter-channel delay registers to add a delay per

channel from 0 to 255 clock cycles. The delays correspond to cycles of the high-speed internal clock, DCLK.

The default values are shown in Table 2 - 9.

Table 2 - 9. Inter-Channel Delay Default Values

I2C SUB-ADDRESS

CHANNEL

INTER-CHANNEL DELAY DEFAULT (DCLK PERIODS)

0x1B

-24

0x1C

0x1D

-16

0x1E

+16

0x1F

-24

0x20

0x21

-8

0x22

+24

TAS5028 Datasheet(PDF) 39 Page - Texas Instruments

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