TAS5028 datasheet(55/84 Pages) TI

55 / 84 page

I2C Serial Control Interface (Slave Address 0x36)

SLES112 — June 2004

TAS5028

When the correct number of bytes has been received, the TAS5028 starts processing the data.

The procedure to perform an incremental multi-byte write operation is as follows:

Start a normal I2C write operation by sending the device address, write bit, register subaddress, and the

first four bytes of the data to be written. At the end of that sequence, send a stop condition. At this point,

the register has been opened and accepts the remaining data that is sent by writing 4-byte blocks of data

to the append subaddress (0xFE).

At a later time, one or more append data transfers are performed to incrementally transfer the remaining

number of bytes in sequential order to complete the register write operation. Each of these append

operations will be composed of the device address, write bit, append subaddress (0xFE), and four bytes

of data followed by a stop condition.

The operation will be terminated due to an error condition and the data will be flushed:

If a new subaddress is written to the TAS5028 before the correct number of bytes have been written.

If more or less than 4 bytes are data written at the beginning or during any of the append operations.

If a read bit is sent.

4.6

Single Byte Read

As shown in Figure 4 - 4, a single byte data read transfer begins with the master device transmitting a start

condition followed by the I2C device address and the read/write bit. For the data read transfer, both a write

followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal

memory address to be read. As a result, the read/write bit will be a 0. After receiving the TAS5028 address

and the read/write bit, the TAS5028 responds with an acknowledge bit. In addition, after sending the internal

memory address byte or bytes, the master device transmits another start condition followed by the TAS5028

address and the read/write bit again. This time the read/write bit will be a 1, indicating a read transfer. After

receiving the TAS5028 and the read/write bit the TAS5028 again responds with an acknowledge bit. Next, the

TAS5028 transmits the data byte from the memory address being read. After receiving the data byte, the

master device transmits a not acknowledge followed by a stop condition to complete the single byte data read

transfer.

A0 R/W ACK A7

A0 ACK

ACK

Start

Condition

Stop

Condition

Acknowledge

I2C Device Address and

Read/Write Bit

Sub-Address

Data Byte

D0 ACK

I2C Device Address and

Read/Write Bit

Not

Acknowledge

R/W

Repeat Start

Condition

Figure 4 - 4. Single Byte Read Transfer

4.7

Multiple Byte Read

A multiple byte data read transfer is identical to a single byte data read transfer except that multiple data bytes

are transmitted by the TAS5028 to the master device as shown in Figure 4 - 5. Except for the last data byte,

the master device responds with an acknowledge bit after receiving each data byte.

ACK

Acknowledge

I2C Device Address and

Read/Write Bit

R/W

A0 R/W ACK

ACK

D0 ACK

Start

Condition

Stop

Condition

Acknowledge

Last Data Byte

ACK

First Data Byte

Repeat Start

Condition

Not

Acknowledge

I2C Device Address and

Read/Write Bit

Sub-Address

Other Data Bytes

D0 ACK

Acknowledge

Figure 4 - 5. Multiple Byte Read Transfer

TAS5028 Datasheet(PDF) 55 Page - Texas Instruments

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