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TAS5028 Datasheet(PDF) 74 Page - Texas Instruments |
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TAS5028 Datasheet(HTML) 74 Page - Texas Instruments |
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74 / 84 page ![]() Serial Control Interface Register Definitions 66 SLES112 — June 2004 TAS5028 Table 6 - 24. Treble and Bass Gain Step Size (Slew Rate) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION 0 0 0 0 0 0 0 0 No operation 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 Minimum rate – Updates every 0.083 ms (every LRCLK at 48 kHz) 0 0 1 0 0 0 0 0 Update ever 0.67 ms (32 LRCLKs at 48 kHz) 0 0 1 1 1 1 1 1 Default rate - Updates every 1.31 ms (63 LRCLKs at 48 kHz). This is the maximum constant time that can be set for all sample rates. 1 1 1 1 1 1 1 1 Minimum rate – Updates every 5.08 ms (every 255 LRCLKs at 48 kHz) 6.20 Volume Registers (0xD1 - 0xD9) Channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into registers 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, and 0xD8. Master volume is mapped into register 0xD9. Bits D31 - D12 are Don’t Care. Table 6 - 25. Volume Registers D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION Unused bits D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION Unused bits D15 D14 D13 D12 D11 D10 D9 D8 FUNCTION V11 V10 V9 V8 Volume D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION V7 V6 V5 V4 V3 V2 V1 V0 Volume |
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