ATMEGA640 datasheet(78/449 Pages) ATMEL

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ATmega640/1280/1281/2560/2561

2549K–AVR–01/07

EICRA – External Interrupt

Control Register A

The External Interrupt Control Register A contains control bits for interrupt sense

control.

• Bits 7:0 – ISC31, ISC30 – ISC00, ISC00: External Interrupt 3 - 0 Sense Control

Bits

The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag

and the corresponding interrupt mask in the EIMSK is set. The level and edges on the

external pins that activate the interrupts are defined in Table 34. Edges on INT3:0 are

registered asynchronously. Pulses on INT3:0 pins wider than the minimum pulse width

given in Table 35 will generate an interrupt. Shorter pulses are not guaranteed to gener-

ate an interrupt. If low level interrupt is selected, the low level must be held until the

completion of the currently executing instruction to generate an interrupt. If enabled, a

level triggered interrupt will generate an interrupt request as long as the pin is held low.

When changing the ISCn bit, an interrupt can occur. Therefore, it is recommended to

first disable INTn by clearing its Interrupt Enable bit in the EIMSK Register. Then, the

ISCn bit can be changed. Finally, the INTn interrupt flag should be cleared by writing a

logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the interrupt is re-

enabled.

Note:

1. n = 3, 2, 1or 0.

When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its

Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when

the bits are changed.

Bit

7654

321

(0x69)

ISC31

ISC30

ISC21

ISC20

ISC11

ISC10

ISC01

ISC00

EICRA

Read/Write

R/W

Initial Value

0000

000

Table 34. Interrupt Sense Control

(1)

ISCn1

ISCn0

Description

The low level of INTn generates an interrupt request.

Any edge of INTn generates asynchronously an interrupt request.

The falling edge of INTn generates asynchronously an interrupt request.

The rising edge of INTn generates asynchronously an interrupt request.

Table 35. Asynchronous External Interrupt Characteristics

Symbol

Parameter

Condition

Min

Typ

Max

Units

tINT

Minimum pulse width for

asynchronous external interrupt

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