ATMEGA640 datasheet(27/449 Pages) ATMEL

27 / 449 page

ATmega640/1280/1281/2560/2561

2549K–AVR–01/07

For details about the port override, see the alternate functions in section “I/O-Ports” on

page 83. The XMEM interface will auto-detect whether an access is internal or external.

If the access is external, the XMEM interface will output address, data, and the control

signals on the ports according to Figure 15 (this figure shows the wave forms without

wait-states). When ALE goes from high-to-low, there is a valid address on AD7:0. ALE is

low during a data transfer. When the XMEM interface is enabled, also an internal access

will cause activity on address, data and ALE ports, but the RD and WR strobes will not

toggle during internal access. When the External Memory Interface is disabled, the nor-

mal pin and data direction settings are used. Note that when the XMEM interface is

disabled, the address space above the internal SRAM boundary is not mapped into the

internal SRAM. Figure 14 illustrates how to connect an external SRAM to the AVR using

an octal latch (typically “74 x 573” or equivalent) which is transparent when G is high.

Address Latch Requirements

Due to the high-speed operation of the XRAM interface, the address latch must be

selected with care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V.

When operating at conditions above these frequencies, the typical old style 74HC series

latch becomes inadequate. The External Memory Interface is designed in compliance to

the 74AHC series latch. However, most latches can be used as long they comply with

the main timing parameters. The main parameters for the address latch are:

•

D to Q propagation delay (t

PD).

•

Data setup time before G low (t

SU).

•

Data (address) hold time after G low (

TH).

The External Memory Interface is designed to guaranty minimum address hold time

after G is asserted low of t

h = 5 ns. Refer to tLAXX_LD/tLLAXX_ST in “External Data Memory

Timing” Tables 173 through Tables 180 on pages 385 - 387. The D-to-Q propagation

delay (t

PD) must be taken into consideration when calculating the access time require-

ment of the external component. The data setup time before G low (t

SU) must not

exceed address valid to ALE low (t

AVLLC) minus PCB wiring delay (dependent on the

capacitive load).

Figure 14. External SRAM Connected to the AVR

D[7:0]

A[7:0]

A[15:8]

SRAM

AD7:0

ALE

A15:8

AVR

ATMEGA640 Datasheet(PDF) 27 Page - ATMEL Corporation

ATMEGA640 Datasheet(HTML) 27 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL