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ATMEGA640 Datasheet(PDF) 79 Page - ATMEL Corporation |
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ATMEGA640 Datasheet(HTML) 79 Page - ATMEL Corporation |
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79 / 449 page  79 ATmega640/1280/1281/2560/2561 2549K–AVR–01/07 EICRB – External Interrupt Control Register B • Bits 7:0 – ISC71, ISC70 - ISC41, ISC40: External Interrupt 7 - 4 Sense Control Bits The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined in Table 36. The value on the INT7:4 pins are sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. Note: 1. n = 7, 6, 5 or 4. When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed. EIMSK – External Interrupt Mask Register • Bits 7:0 – INT7:0: External Interrupt Request 7 - 0 Enable When an INT7:0 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt Control Registers – EICRA and EICRB – defines whether the external interrupt is activated on rising or falling edge or level sensed. Activity on any of these pins will trigger an interrupt request even if the pin is enabled as an output. This provides a way of generating a software interrupt. Bit 7654 321 0 (0x6A) ISC71 ISC70 ISC61 ISC60 ISC51 ISC50 ISC41 ISC40 EICRB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0000 000 0 Table 36. Interrupt Sense Control(1) ISCn1 ISCn0 Description 0 0 The low level of INTn generates an interrupt request. 0 1 Any logical change on INTn generates an interrupt request 10 The falling edge between two samples of INTn generates an interrupt request. 11 The rising edge between two samples of INTn generates an interrupt request. Bit 7654 321 0 0x1D (0x3D) INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 EIMSK Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0000 000 0 |
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