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ATMEGA640 Datasheet(PDF) 81 Page - ATMEL Corporation |
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ATMEGA640 Datasheet(HTML) 81 Page - ATMEL Corporation |
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81 / 449 page  81 ATmega640/1280/1281/2560/2561 2549K–AVR–01/07 PCIFR – Pin Change Interrupt Flag Register • Bit 2 – PCIF2: Pin Change Interrupt Flag 1 When a logic change on any PCINT23:16 pin triggers an interrupt request, PCIF2 becomes set (one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter- rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. • Bit 1 – PCIF1: Pin Change Interrupt Flag 1 When a logic change on any PCINT15:8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter- rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. • Bit 0 – PCIF0: Pin Change Interrupt Flag 0 When a logic change on any PCINT7:0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter- rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. PCMSK2 – Pin Change Mask Register 2 • Bit 7:0 – PCINT23:16: Pin Change Enable Mask 23:16 Each PCINT23:16-bit selects whether pin change interrupt is enabled on the corre- sponding I/O pin. If PCINT23:16 is set and the PCIE2 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT23:16 is cleared, pin change interrupt on the corresponding I/O pin is disabled. PCMSK1 – Pin Change Mask Register 1 • Bit 7:0 – PCINT15:8: Pin Change Enable Mask 15:8 Each PCINT15:8-bit selects whether pin change interrupt is enabled on the correspond- ing I/O pin. If PCINT15:8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT15:8 is cleared, pin change interrupt on the corresponding I/O pin is disabled. Bit 7 654 32 10 0x1B (0x3B) – – – – – PCIF2 PCIF1 PCIF0 PCIFR Read/Write RR RR R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 765 43 210 (0x6D) PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 PCMSK2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 543 21 0 (0x6C) PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 PCMSK1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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